ADV7195KST datasheet(17/36 Pages) AD

17 / 36 page

REV. A

ADV7195

–17–

MODE REGISTER 2

MR1 (MR27–MR20)

(Address (SR4–SR0) = 02H)

Figure 22 shows the various operations under the control of

Mode Register 2.

MR2 BIT DESCRIPTION

Y Delay (MR20–MR22)

This control bit delays the Y signal with respect to the falling

edge of the horizontal sync signal by up to four pixel clock

cycles. Figure 21 demonstrates this facility.

Color Delay (MR23–MR25)

This control allows delay of the color signals with respect to the

falling edge of the horizontal sync signal by up to four pixel

clock cycles. Figure 21 demonstrates this facility.

CGMS Enable (MR26)

When this bit is set to “1,” CGMS data is inserted on Line

41 in 525p mode. The CGMS conforms to CGMS-A EIA-J

CPR1204-1, Transfer Method of Video ID information using

vertical blanking interval (525p System), March 1998 and

IEC61880, 1998, video systems (525/60)—video and accompanied

data using the vertical blanking interval—analog interface.

The CGMS data bits are programmed into the CGMS Data

Registers 0–2. For more information refer to CGMS Data

Registers section.

CGMS CRC (MR27)

This bit enables the automatic Cyclic Redundancy Check when

CGMS is enabled.

Y DELAY

PrPb DELAY

MAX

DELAY

NO DELAY

MAX DELAY

NO DELAY

Y OUTPUT

PrPb OUTPUT

Figure 21. Y and Color Delay

MR27

MR26

MR25

MR24

MR23

MR22

MR21

MR20

CGMS ENABLE

DISABLE

ENABLE

MR26

COLOR DELAY

0 PCLK

1 PCLK

2 PCLK

3 PCLK

4 PCLK

MR25

DISABLE

ENABLE

MR27

CGMS CRC

MR24 MR23

Y DELAY

0 PCLK

1 PCLK

2 PCLK

3 PCLK

4 PCLK

MR22 MR21 MR20

Figure 22. Mode Register 2

ADV7195KST Datasheet(PDF) 17 Page - Analog Devices

ADV7195KST Datasheet(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL