DSP16210 datasheet(17/173 Pages) AGERE

17 / 173 page

Data Sheet

July 2000

DSP16210 Digital Signal Processor

Lucent Technologies Inc.

DRAFT COPY

Hardware Architecture (continued)

DSP16000 Core Architectural Overview (continued)

Table 2. DSP16000 Core Block Diagram Legend

Symbol

Name

16 x 16 MULTIPLY 16-bit x 16-bit Multiplier

a0—a7

Accumulators 0—7

ADDER

3-input 40-bit Adder/Subtractor

alf

AWAIT and Flags

ALU/ACS

40-bit Arithmetic Logic Unit and Add/Compare/Select Function—used in Viterbi decoding

ar0—ar3

Auxiliary Registers 0—3

auc0, auc1

Arithmetic Unit Control Registers

BMU

40-bit Bit Manipulation Unit

c0, c1

Counters 0 and 1

Counter Holding Register

cloop

Cache Loop Count

COMPARE

Comparator

csave

Cache Save Register

cstate

Cache State Register

DAU

Data Arithmetic Unit

Pointer Postincrement Register for the X-Memory Space

IDB

Internal Data Bus

inc0, inc1

Interrupt Control Registers 0 and 1

ins

Interrupt Status Register

Pointer Postincrement/Offset Register for the Y-Memory Space

MUX

Multiplexer

p0, p1

Product Registers 0 and 1

Program Counter

Program Interrupt Return Register

Program Return Register

PSG

Pseudorandom Sequence Generator

psw0, psw1

Processor Status Word Registers 0 and 1

pt0, pt1

Pointers 0 and 1 to X-Memory Space

ptrap

Program Trap Return Register

r0—r7

Pointers 0—7 to Y-Memory Space

rb0, rb1

Circular Buffer Pointers 0 and 1 (begin address)

re0, re1

Circular Buffer Pointers 0 and 1 (end address)

SAT

Saturation

SHIFT

Shifting Operation

Stack Pointer

SPLIT/MUX

Split/Multiplexer—routes the appropriate ALU/ACS, BMU, and ADDER outputs to the appro-

priate accumulator

SWAP MUX

Swap Multiplexer—routes the appropriate data to the appropriate multiplier input

SYS

System Control and Cache

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