DSP16210 datasheet(49/173 Pages) AGERE

49 / 173 page

Data Sheet

July 2000

DSP16210 Digital Signal Processor

Lucent Technologies Inc.

DRAFT COPY

Hardware Architecture (continued)

Simple Serial I/O (SSIO) Unit

The SSIO provides a 26 Mbits/s serial interface to

many codecs and signal processors with few, if any,

additional components. The high-speed, double-buff-

ered port supports back-to-back transmissions of data.

The SSIO is configurable as active or passive and is a

DMA peripheral that interfaces to IORAM1 through

MIOU1.

There are four active clock speeds selectable by ACLK

(bits 7 and 8) of the simple serial I/O control register

(SSIOC). (See Table 70 on page 110.)

A bit-reversal mode under control of SSIOC register

bit 6 provides compatibility with either the most signifi-

cant bit (MSB) first or least significant bit (LSB) first

serial I/O formats.

The serial data can be internally looped back (DO

looped back to DI) by setting the SSIO loopback con-

trol bit, SIOLB (bit 9) of the ioc register. SIOLB affects

only the SSIO.

Setting data out delay (DODLY), bit 10, of SSIOC to 1

delays DO by one phase of OCK so that DO changes

on the falling edge of OCK instead of the rising edge

(DODLY = 0). This reduces the time available for DO to

drive DI and to be valid for the rising edge of ICK, but

increases the hold time on DO by half a cycle of OCK.

A falling edge on the SYNC input pin causes the resyn-

chronization of the active input load (ILD) and output

load (OLD) generators. This input has typically 0.7 V

hysteresis. If SYNC is not used, it must be tied low.

Programmable Modes

SSIOC controls the programmable modes of operation

for the SSIO. This register, shown in Table 70 on

page 110, is used to set the port into various configura-

tions. Both input and output operations can be inde-

pendently configured as either active or passive. When

active, the DSP16210 generates load and clock sig-

nals. When passive, load and clock signal pins are

inputs.

Since input and output can be independently config-

ured, the SSIO has four different modes of operation.

The SSIOC register is also used to select the fre-

quency of active clocks for the SSIO. Finally, SSIOC is

used to configure the serial I/O data formats. The data

can be 8 or 16 bits long, and can also be input/output

MSB or LSB first. Input and output data formats can be

independently configured.

The SSIOC register is programmed through MIOU1.

Parallel Host Interface (PHIF16)

The DSP16210 has a 16-bit parallel host bus interface

for rapid transfer of data with external devices. PHIF16

is a DMA peripheral that interfaces to IORAM0 through

MIOU0.

This parallel port is passive (data strobes provided by

an external device) and supports either

Motorola or

Intel microcontroller protocols. The PHIF16 can be

configured by software to operate with either an 8-bit or

16-bit external interface. (See the PHIFC register,

Table 63 on page 104.)

In 8-bit external configuration, PHIF16 provides for 8-bit

or 16-bit logical data transfers. 8-bit data is right-

justified. As a flexible host interface, it requires little or

no glue logic to interface to other devices (e.g., micro-

controllers, microprocessors, or another DSP).

The logical data path of the PHIF16 consists of a 16-bit

input register, PDX(in), and a 16-bit output register,

PDX(out). PDX(in) is loaded with host data from the

16-bit data bus PB[15:0]. PDX(out) is loaded by MIOU0

with output data from the IORAM0 location addressed

by the MIOU output read pointer 0 (morp0) register.

Two output pins, parallel input buffer full (PIBF) and

parallel output buffer empty (POBE), indicate the state

of the PDX buffers. In addition, there are two registers

used to control and monitor the PHIF's operation: the

parallel host interface control register (PHIFC, see

Table 63 on page 104), and the PHIF16 status register

(PSTAT, see Table 24 on page 51). The PSTAT regis-

ter, which reflects the state of the PIBF and POBE

flags, can only be read by an external device when the

PSTAT input pin is asserted. The PHIFC register

defines the programmable options for this port and is

programmed through MIOU0 using PCTL_LD, the

peripheral control load command (see Table 18 on

page 44).

DSP16210 Datasheet(PDF) 49 Page - Agere Systems

DSP16210 Datasheet(HTML) 49 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL