DSP16210 datasheet(2/173 Pages) AGERE

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Data Sheet

DSP16210 Digital Signal Processor

July 2000

Table of Contents

Contents

Page

Contents

Page

DRAFT COPY

Lucent Technologies Inc.

®Features ................................................................... 1

®Description ............................................................... 1

®Notation Conventions ............................................... 9

®Hardware Architecture ............................................. 9

® DSP16210 Architectural Overview ......................... 9

DSP16000 Core................................................. 9

Clock Synthesizer (PLL) .................................... 9

Dual-Port RAM (DPRAM) .................................. 9

Internal Boot ROM (IROM) .............................. 12

IORAM and Modular I/O Units (MIOUs) .......... 12

External Memory Interface (EMI) ..................... 12

Bit I/O (BIO) Unit .............................................. 13

Enhanced Serial I/O (ESIO) Unit ..................... 13

Simple Serial I/O (SSIO) Unit .......................... 13

Parallel Host Interface (PHIF16) ...................... 13

Timers.............................................................. 13

Test Access Port (JTAG) ................................. 13

Hardware Development System (HDS) ........... 13

Pin Multiplexing................................................ 13

® DSP16000 Core Architectural Overview............... 14

System Control and Cache (SYS) ................... 14

Data Arithmetic Unit (DAU) .............................. 14

Y-Memory Space Address Arithmetic

Unit (YAAU) .................................................. 15

X-Memory Space Address Arithmetic

Unit (XAAU) .................................................. 15

® Reset .................................................................... 18

Reset After Powerup or Power Interruption ..... 18

RSTB Pin Reset............................................... 18

JTAG Controller Reset..................................... 19

® Interrupts and Trap ............................................... 20

Interrupt Registers ........................................... 20

Clearing Interrupts ........................................... 23

Interrupt Request Clearing Latency ................. 23

INT[3:0] and TRAP Pins .................................. 24

Low-Power Standby Mode............................... 24

® Memory Maps ....................................................... 25

Boot from External ROM.................................. 27

Data Memory Map Selection ........................... 27

® External Memory Interface (EMI).......................... 27

Latency for Programming mwait and ioc

Registers....................................................... 27

Programmable Access Time............................ 28

READY Pin Enables ........................................ 28

Enable Delays.................................................. 28

Memory Map Selection .................................... 28

RWN Advance ................................................. 29

CKO Pin Configuration .................................... 29

Write Data Drive Delay .................................... 29

Functional Timing ............................................ 29

READY Pin ...................................................... 31

® Enhanced Serial I/O (ESIO) Unit ..........................32

Input Section .................................................... 32

Output Section ................................................. 36

® Modular I/O Units (MIOUs) ...................................42

IORAM ............................................................. 42

MIOU Registers ............................................... 42

MIOU Commands ............................................43

I/O Buffer Configuration ................................... 45

Length Counters and MIOU Interrupts............. 46

DMA Input Flow Control................................... 46

DMA Output Flow Control ................................ 47

MIOU Performance .......................................... 47

Powering Down an MIOU ................................ 47

MIOU Command Latencies.............................. 48

® Simple Serial I/O (SSIO) Unit ...............................49

Programmable Modes...................................... 49

® Parallel Host Interface (PHIF16)...........................49

Programmability ............................................... 50

® Bit Input/Output Unit (BIO)....................................52

Pin Multiplexing................................................ 53

® Timers...................................................................53

® Hardware Development System (HDS) ................54

® JTAG Test Port .....................................................54

® Clock Synthesis ....................................................56

Phase-Lock Loop (PLL) Operation ..................58

Phase-Lock Loop (PLL) Operating

Frequency ..................................................... 58

Phase-Lock Loop (PLL) Locking...................... 58

Phase-Lock Loop (PLL) Programming

Restrictions ................................................... 59

Phase-Lock Loop (PLL) Programming

Example ........................................................ 60

Phase-Lock Loop (PLL) Frequency

Accuracy and Jitter ....................................... 60

Phase-Lock Loop (PLL) Power Connections ... 60

® Power Management..............................................61

The powerc Control Register Bits ................... 61

STOP Pin ......................................................... 63

PLL Powerdown............................................... 63

AWAIT Bit of the alf Register........................... 63

Power Management Examples ........................63

®Software Architecture .............................................69

® Instruction Set Quick Reference ...........................69

Conditions Based on the State of Flags...........85

® Registers...............................................................86

Peripheral Register Write-Read Latency ......... 86

Reset States .................................................. 113

RB Field Encoding ......................................... 115

®Pin Information .....................................................116

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