DSP16210 datasheet(21/173 Pages) AGERE

21 / 173 page

Data Sheet

July 2000

DSP16210 Digital Signal Processor

Lucent Technologies Inc.

DRAFT COPY

Hardware Architecture (continued)

Interrupts and Trap (continued)

Table 4. Interrupt and User Trap Vector Table

Vector Description

Vector Address†

Priority

VEC[3:0]

Signals‡

Hexadecimal

Decimal

Reserved

vbase + 0x0

vbase + 0

—

PTRAP (driven by TRAP pin)

vbase + 0x4

vbase + 4

6—Highest

0xD

UTRAP (reserved for HDS)

vbase + 0x8

vbase + 8

0xE

Reserved

vbase + 0xC

vbase + 12

—

Reserved

vbase + 0x10

vbase + 16

—

MIBF0

vbase + 0x14

vbase + 20

0—3§

0x1

MOBE0

vbase + 0x18

vbase + 24

0—3§

0x2

MIBF1

vbase + 0x1C

vbase + 28

0—3§

0x3

MOBE1

vbase + 0x20

vbase + 32

0—3§

0x4

INT0

vbase + 0x24

vbase + 36

0—3§

0x5

INT1

vbase + 0x28

vbase + 40

0—3§

0x6

INT2

vbase + 0x2C

vbase + 44

0—3§

0x7

INT3

vbase + 0x30

vbase + 48

0—3§

0x8

TIME0

vbase + 0x34

vbase + 52

0—3§

0x9

TIME1

vbase + 0x38

vbase + 56

0—3§

0xA

EIFE

vbase + 0x3C

vbase + 60

0—3§

0xB

EOFE

vbase + 0x40

vbase + 64

0—3§

0xC

ECOL

vbase + 0x44

vbase + 68

0—3§

0xD

EIBF

vbase + 0x48

vbase + 72

0—3§

0xE

EOBE

vbase + 0x4C

vbase + 76

0—3§

0xF

Reserved

vbase + 0x50

vbase + 80

—

Reserved

vbase + 0x54

vbase + 84

—

Reserved

vbase + 0x58

vbase + 88

—

Reserved

vbase + 0x5C

vbase + 92

—

Software Interrupt 0 (icall 0)

vbase + 0x60

vbase + 96

—

0xC

Software Interrupt 1 (icall 1)

vbase + 0x64

vbase + 100

—

0xC

—0xC

Software Interrupt 62 (icall 62)

vbase + 0x158

vbase + 344

—

0xC

Software Interrupt 63 (icall 63)

vbase + 0x15C

vbase + 348

—

0xC

† vbase contains the base address of the 352-word vector table.

‡ The VEC[3:0] signals are multiplexed with the BIO signals IOBIT[7:4] onto the VEC[3:0]/IOBIT[7:4] pins (VEC0 corresponds to IOBIT7, VEC1

corresponds to IOBIT6, VEC2 corresponds to IOBIT5, and VEC3 corresponds to IOBIT4). VEC[3:0] defaults to 0xF (all ones) if the core is not

currently servicing an interrupt or a trap.

§ The programmer specifies the relative priority levels 0—3 for hardware interrupts via inc0 and inc1 (see the

DSP16000 Digital Signal Proces-

sor Core Information Manual). Level 0 indicates a disabled interrupt. If the core simultaneously recognizes more than one interrupt with the

same assigned priority, it services the interrupt with the lowest vector address first.

DSP16210 Datasheet(PDF) 21 Page - Agere Systems

DSP16210 Datasheet(HTML) 21 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL