DSP16210 datasheet(48/173 Pages) AGERE

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Data Sheet

DSP16210 Digital Signal Processor

July 2000

DRAFT COPY

Lucent Technologies Inc.

Hardware Architecture (continued)

Modular I/O Units (MIOUs) (continued)

MIOU Command Latencies

As a consequence of the pipelined IDB (internal data bus), there is a write-to-read latency for data move instruc-

tions that access peripheral (off-core) registers. DSP initiated MIOU operations incur a delay before completion of

the operation can be observed in a DSP flag or register. These latencies are summarized in Table 21.

Table 21. MIOU Command Latencies

MIOU Command†

† Key to these columns: REG is any register, MEM is any memory location, ILEN_UP is a value (immediate, register contents, or memory loca-

tion contents) such that bits [15:12] are 0x4, OLEN_UP is a value (immediate, register contents, or memory location contents) such that bits

[15:12] are 0x5, and INSTR is any conditional instruction.

Subsequent

Instruction†

Latency

(Cycles)

Example

mcmd

〈0,1〉 =

〈ILEN_UP, OLEN_UP, RESET〉

ireturn

(return from interrupt

service routine)

mcmd0=0x4010

4*nop

ireturn

ILEN_UP command clears

MIBF0 request. 4 nops are

needed to avoid uninten-

tional re-entry into ISR.

ins =

〈REG, MEM〉

(clear interrupt pending

bit within a polling rou-

tine)

mcmd1=0x6000

6*nop

ins=0x00008

a0=ins

RESET command clears

MIBF1 request and sets

MOBE1 request. 6 nops

are needed before MIBF1

bit in ins can be cleared.

mcmd

〈0,1〉 = OLEN_UP

〈REG, MEM〉 = alf

(poll MBUSY1 in alf)

mcmd1=0x5001

5*nop

if mbusy1 goto wait

Five instruction cycles are

required between an OLEN

update and the test of the

MBUSY1 flag for comple-

tion of the corresponding

output operation.

if mbusy

〈0,1〉 INSTR

(poll MBUSY1 with con-

ditional instruction.)

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