AD5689 datasheet(5/24 Pages) AD

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Data Sheet

AD5689/AD5687

Rev. 0 | Page 5 of 24

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.

VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 4.

1.8 V ≤ VLOGIC <

2.7 V

2.7 V ≤ VLOGIC ≤

5.5 V

Parameter1

Min

Max

Min

Max

Unit

Description

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge setup time

Data setup time

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time (update single channel or both channels)

SYNC falling edge to SCLK fall ignore

t10

LDAC pulse width low

t11

SCLK falling edge to LDAC rising edge

t12

SCLK falling edge to LDAC falling edge

t13

RESET minimum pulse width low

t14

RESET pulse activation time

Power-Up Time

4.5

µs

Time that is required to exit power-down mode and enter

normal mode of operation; 24th clock edge to 90% of DAC

midscale value with output unloaded

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 2.7 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.

Figure 2. Serial Write Operation

SCLK

SYNC

SDIN

DB23

t10

t11

LDAC1

LDAC2

t12

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

RESET

t13

t14

VOUTX

DB0

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