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ADF4159 Datasheet(PDF) 4 Page - Analog Devices

Part # ADF4159
Description  Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer
PDF  36 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4159 Datasheet(HTML) 4 Page - Analog Devices

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ADF4159
Data Sheet
Rev. B | Page 4 of 36
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor3
PLL loop BW = 1 MHz
Integer-N Mode
−224
dBc/Hz
FRAC = 0
Fractional-N Mode
−217
dBc/Hz
Normalized 1/f Noise (PN1_f)4
−120
dBc/Hz
Measured at 10 kHz offset, normalized
to 1 GHz
Phase Noise Performance5
At VCO output
12,002 MHz Output6
−96
dBc/Hz
At 50 kHz offset, 100 MHz PFD frequency
1
Operating temperature: −40°C to +125°C.
2
Guaranteed by design. Sample tested to ensure compliance.
3
This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(fPFD) + 20 logN) to calculate
in-band phase noise performance as seen at the VCO output.
4
The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at an offset frequency (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
5
The phase noise is measured with the EV-ADF4159EB3Z and the Rohde & Schwarz FSUP signal source analyzer.
6
fREFIN = 100 MHz; fPFD = 100 MHz; offset frequency = 50 kHz; RFOUT = 12,002 MHz; N = 120.02; loop bandwidth = 250 kHz.
TIMING SPECIFICATIONS
AVDD = VP = 2.7 V to 3.45 V, DVDD = SDVDD = 1.8 V, AGND = DGND = SDGND = CPGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω,
unless otherwise noted.
Table 2. Write Timing
Parameter
Limit at TMIN to TMAX
Unit
Description
t1
20
ns min
LE setup time
t2
10
ns min
DATA to CLK setup time
t3
10
ns min
DATA to CLK hold time
t4
25
ns min
CLK high duration
t5
25
ns min
CLK low duration
t6
10
ns min
CLK to LE setup time
t7
20
ns min
LE pulse width
Write Timing Diagram
CLK
DATA
LE
LE
DB30
DB1
(CONTROL BIT C2)
DB2
(CONTROL BIT C3)
DB0 (LSB)
(CONTROL BIT C1)
t1
t2
t3
t4
t5
t7
t6
DB31 (MSB)
Figure 2. Write Timing Diagram



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