ADF4159 datasheet(11/36 Pages) AD

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Data Sheet

ADF4159

Rev. B | Page 11 of 36

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 21 shows a simplified sche-

matic of the PFD.

CLR2

DOWN

HIGH

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Figure 21. PFD Simplified Schematic

The PFD includes a fixed delay element that sets the width of the

antibacklash pulse, which is typically 1 ns. This pulse ensures that

there is no dead zone in the PFD transfer function and gives a

consistent reference spur level.

MUXOUT AND LOCK DETECT

The multiplexer output on the ADF4159 allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by the M4, M3, M2, and M1 bits in

section in block diagram form.

MUXOUT

THREE-S TATE OUTPUT

N DIVIDER OUTPUT

DGND

R DIVIDER OUTPUT

DIGITAL LOCK DETECT

READBACK TO MUXOUT

CLK DIVIDER OUTPUT

SERIAL DATA OUTPUT

R DIVIDER/2

N DIVIDER/2

CONTROL

MUX

DVDD

Figure 22. MUXOUT Schematic

INPUT SHIFT REGISTER

The ADF4159 digital section includes a 5-bit R counter, a 12-bit

INT counter, and a 25-bit FRAC counter. Data is clocked into the

32-bit input shift register on each rising edge of CLK. The data

is clocked in MSB first. Data is transferred from the input shift

The destination latch is determined by the state of the three

control bits (C3, C2, and C1) in the input shift register. As shown

in Figure 2, the control bits are the three LSBs (DB2, DB1, and

DB0, respectively). Table 7 shows the truth table for these bits.

Figure 23 and Figure 24 provide a summary of how the latches

are programmed.

Table 7. Truth Table for the C3, C2, and C1 Control Bits

Control Bits

PROGRAM MODES

Table 7 and Figure 25 through Figure 32 show how the program

modes are set up in the ADF4159.

The following settings in the ADF4159 are double buffered:

LSB fractional value, phase value, charge pump current setting,

reference divide-by-2, reference doubler, R counter value, and

CLK1 divider value. Before the part uses a new value for any

double-buffered setting, the following two events must occur:

1. The new value is latched into the device by writing to the

appropriate register.

2. A new write is performed to Register 0 (R0).

For example, updating the fractional value involves a write to

the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 must be

written to first, followed by the write to R0. The frequency change

begins after the write to R0. Double-buffering ensures that the

bits written to R1 do not take effect until after the write to R0.

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