ADF4159

Data Sheet

Rev. B | Page 14 of 36

FRAC/INT REGISTER (R0) MAP

When Bits DB[2:0] are set to 000, the on-chip FRAC/INT

register (Register R0) is programmed (see Figure 25).

Ramp On

When Bit DB31 is set to 1, the ramp function is enabled. When

Bit DB31 is set to 0, the ramp function is disabled.

MUXOUT Control

The on-chip multiplexer of the ADF4159 is controlled by

Bits DB[30:27]. See Figure 25 for the truth table.

12-Bit Integer Value (INT)

Bits DB[26:15] set the INT value, which forms part of the overall

feedback division factor. For more information, see the INT, FRAC,

and R Counter Relationship section.

12-Bit MSB Fractional Value (FRAC)

Bits DB[14:3], along with Bits DB[27:15] in the LSB FRAC register

(Register R1), set the FRAC value that is loaded into the fractional

interpolator. The FRAC value forms part of the overall feedback

division factor. These 12 bits are the most significant bits (MSBs)

of the 25-bit FRAC value; Bits DB[27:15] in the LSB FRAC register

(Register R1) are the least significant bits (LSBs). For more infor-

mation, see the RF Synthesizer Worked Example section.

DB31

CONTROL

BITS

12-BIT MSB FRACTIONAL VALUE

(FRAC)

12-BIT INTEGER VALUE (INT)

MUXOUT

CONTROL

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R1

M4

M3

M2

M1

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

F25

F24

F23

F22

F21

F20

F19

F18

F17

F16

F15

F14 C3(0) C2(0) C1(0)

M4 M3 M2

M1

OUTPUT

0

0

0

0

THREE-STATE OUTPUT

0

0

0

1

0

0

1

0

DGND

0

0

1

1

R DIVIDER OUTPUT

0

1

0

0

N DIVIDER OUTPUT

0

1

0

1

RESERVED

0

1

1

0

DIGITAL LOCK DETECT

0

1

1

1

SERIAL DATA OUTPUT

1

0

0

0

RESERVED

1

0

0

1

RESERVED

1

0

1

0

CLK DIVIDER OUTPUT

1

0

1

1

RESERVED

1

1

0

0

RESERVED

1

1

0

1

R DIVIDER/2

1

1

1

0

N DIVIDER/2

1

1

1

1

READBACK TO MUXOUT

R1 RAMP ON

0

RAMP DISABLED

RAMP ENABLED

1

F25

F24

...

F15

F14

MSB FRACTIONAL VALUE

(FRAC)*

0

1

2

3

.

.

.

4092

4093

4094

4095

0

0

0

0

.

.

.

1

1

1

1

0

0

0

0

.

.

.

1

1

1

1

...

...

...

...

...

...

...

...

...

...

...

0

0

1

1

.

.

.

0

0

1

1

0

1

0

1

.

.

.

0

1

0

1

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

INTEGER VALUE (INT)

0

0

0

0

0

0

0

1

0

1

1

1

23

0

0

0

0

0

0

0

1

1

0

0

0

24

0

0

0

0

0

0

0

1

1

0

0

1

25

0

0

0

0

0

0

0

1

1

0

1

0

26

.

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1

1

1

1

1

1

1

1

1

1

0

1

4093

1

1

1

1

1

1

1

1

1

1

1

0

4094

1

1

1

1

1

1

1

1

1

1

1

1

4095

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

REGISTER R0 AND THE 13-BIT LSB STORED IN REGISTER R1.

Figure 25. FRAC/INT Register (R0) Map