FX3 datasheet(7/45 Pages) CYPRESS

7 / 45 page

CYUSB301X

Document Number: 001-52136 Rev. *N

Page 7 of 45

Figure 5. Carkit UART Pass-through Block Diagram

GPIF II

The high-performance GPIF II interface enables functionality

similar to, but more advanced than, FX2LP’s GPIF and Slave

FIFO interfaces.

The GPIF II is a programmable state machine that enables a

flexible interface that may function either as a master or slave in

industry-standard or proprietary interfaces. Both parallel and

serial interfaces may be implemented with GPIF II.

Here are a list of GPIF II features:

■ Functions as master or slave

■ Provides 256 firmware programmable states

■ Supports 8-bit, 16-bit, and 32-bit parallel data bus

■ Enables interface frequencies up to 100 MHz

■ Supports 14 configurable control pins when a 32- bit data bus

is used. All control pins can be either input/output or bidirec-

tional.

■ Supports 16 configurable control pins when a 16/8 data bus is

used. All control pins can be either input/output or bi-directional.

GPIF II state transitions are based on control input signals. The

control output signals are driven as a result of the GPIF II state

transitions. The INT# output signal can be controlled by GPIF II.

Refer to the GPIFII Designer tool. The GPIF II state machine’s

behavior is defined by a GPIF II descriptor. The GPIF II

descriptor is designed such that the required interface specifica-

tions are met. 8 kB of memory (separate from the 512 kB of

embedded SRAM) is dedicated to the GPIF II waveform where

the GPIF II descriptor is stored in a specific format.

Cypress’s GPIFII Designer Tool enables fast development of

GPIF II descriptors and includes examples for common inter-

faces.

Example implementations of GPIF II are the asynchronous slave

FIFO and synchronous slave FIFO interfaces.

Slave FIFO interface

The Slave FIFO interface signals are shown in Figure 6. This

interface allows an external processor to directly access up to

four buffers internal to FX3. Further details of the Slave FIFO

interface are described on page 27.

Note Access to all 32 buffers is also supported over the slave

FIFO interface. For details, contact Cypress Applications

Support.

Figure 6. Slave FIFO Interface

CPU

FX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU.

The core has direct access to 16 kB of Instruction Tightly

Coupled Memory (TCM) and 8 kB of Data TCM. The

ARM926EJ-S core provides a JTAG interface for firmware

debugging.

FX3 offers the following advantages:

■ Integrates 512 KB of embedded SRAM for code and data and

8 kB of Instruction cache and Data cache.

■ Implements efficient and flexible DMA connectivity between the

various peripherals (such as, USB, GPIF II, I2S, SPI, UART),

requiring firmware only to configure data accesses between

peripherals, which are then managed by the DMA fabric.

■ Allows easy application development on industry-standard

development tools for ARM926EJ-S.

Examples of the FX3 firmware are available with the Cypress

EZ-USB FX3 Development Kit. Software APIs that can be ported

to an external processor are available with the Cypress EZ-USB

FX3 Software Development Kit.

Carkit UART Pass-through

Interface on GPIF II

()

RXD(DP)

TXD(DM)

USB PHY

TXD

RXD

UART_ TXD

UART_ RXD

GPIO[48]

(UART_TX)

GPIO[49]

( UART_RX)

Carkit UART Pass-through

Interface on GPIOs

External

Processor

EZ-USB FX3

SLCS#

A[1:0]

D[31:0]

SLRD#

SLOE#

SLWR#

PKTEND

FLAGA

FLAGB

Note: Multiple Flags may be configured.

FX3 Datasheet(PDF) 7 Page - Cypress Semiconductor

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