FX3 datasheet(30/45 Pages) CYPRESS

30 / 45 page

CYUSB301X

Document Number: 001-52136 Rev. *N

Page 30 of 45

Figure 14. Asynchronous Slave FIFO Read Mode

Asynchronous Slave FIFO Write Sequence

Description

■ FIFO address is driven and SLCS# is asserted

■ SLWR# is asserted. SLCS# must be asserted with SLWR# or

before SLWR# is asserted

■ Data must be present on the tWRS bus before the deasserting

edge of SLWR#

■ Deassertion of SLWR# causes the data to be written from the

data bus to the FIFO, and then the FIFO pointer is incremented

■ The FIFO flag is updated after the tWFLG from the deasserting

edge of SLWR.

The same sequence of events is shown for a burst write.

Note that in the burst write mode, after SLWR# deassertion, the

data is written to the FIFO, and then the FIFO pointer is incre-

mented.

Short Packet: A short packet can be committed to the USB host

by using the PKTEND#. The external device or processor should

be designed to assert the PKTEND# along with the last word of

data and SLWR# pulse corresponding to the last word. The

FIFOADDR lines must be held constant during the PKTEND#

assertion.

Zero-Length Packet: The external device or processor can

signal a zero-length packet (ZLP) to FX3 simply by asserting

PKTEND#, without asserting SLWR#. SLCS# and the address

must be driven as shown in Figure 15 on page 31.

FLAG Usage: The FLAG signals are monitored by the external

processor for flow control. FLAG signals are FX3 outputs that

can be configured to show empty, full, and partial status for a

dedicated address or the current address.

FIFO ADDR

tAS

SLCS

SLRD

tRDl

SLOE

FLAGA

dedicated thread Flag for An

(1=Not empty 0 = Empty)

tOE

Data Out

High-Z

tAH

DN(An)

tRDO

tOE

tRDO

tOH

tRDh

tRDO

tLZ

DN(An)

DN(Am)

DN+1(Am)

DN+2(Am)

SLWR

(HIGH)

FLAGB

dedicated thread Flag for Am

(1=Not empty 0 = Empty)

tRFLG

tFLG

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