MPC9600AE datasheet(6/15 Pages) IDT

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MPC9600 REVISION 6 JANUARY 7, 2013

MPC9600 Data Sheet

LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER

Table 7. AC Characteristics – 48 LQFP (VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, TA = –40°C to +85°C)(1)

1. AC characteristics are applicable over the entire ambient temperature and supply voltage range and are production tested. AC

characteristics apply for parallel output termination of 50

 to VTT.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency

 8 feedback (FSEL_FB = 0)

 12 feedback (FSEL_FB = 1)

Static test mode (VCCA = GND)

16.67

500

MHz

PLL locked

VCCA = GND

fVCO

VCO Frequency

200

400

MHz

fMAX

Maximum Output Frequency

 2 outputs (FSELx = 0)

 4 outputs (FSELx = 1)

100

200

100

MHz

PLL locked

frefDC

Reference Input Duty Cycle

VPP

Peak-to-Peak Input Voltage

PCLK, PCLK

500

1000

LVPECL

VCMR(2)

2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().

Common Mode Range

PCLK, PCLK (VCC = 3.3 V 5%)

PCLK, PCLK (VCC = 2.5 V 5%)

1.2

VCC –0.8

VCC –0.6

LVPECL

tr, tf

CCLK Input Rise/Fall Time

1.0

see Figure 11

t()

Propagation Delay (static phase offset)

CCLK to FB_IN

PECL_CLK to FB_IN

–60

+30

+40

+130

+140

+230

PLL locked

tsk(o)

Output-to-Output Skew

all outputs, single frequency

all outputs, multiple frequency

within QAx output bank

within QBx outputs

within QCx outputs

150

125

Measured at

coincident rising

edge

Output Duty Cycle

tr, tf

Output Rise/Fall Time

0.1

1.0

see Figure 11

tPLZ, HZ

Output Disable Time

tPZL, ZH

Output Enable Time

PLL Closed Loop Bandwidth

 8 feedback (FSEL_FB=0)

 12 feedback (FSEL_FB=1)

1.0 – 10

0.6 – 4.0

MHz

–3 dB point of PLL

transfer

characteristic

tJIT(CC)

Cycle-to-Cycle Jitter(3)

All outputs in

2 configuration

All outputs in

4 configuration

130

180

Refer to

application

section for other

configurations

tJIT(PER)

Period Jitter(3)

All outputs in

2 configuration

All outputs in

4 configuration

3. Cycle-to-cycle and period jitter depends on output divider configuration.

100

Refer to

application

section for other

configurations

tJIT()

I/O Phase Jitter (1

)VCC = 3.3 V

VCC = 2.5 V

17(4)

15(3)

4. See Applications Information section for max I/O phase jitter versus frequency.

RMS value at

fVCO = 400 MHz

tLOCK

Maximum PLL Lock Time

5.0

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