MPC9600 REVISION 6 JANUARY 7, 2013

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©2013 Integrated Device Technology, Inc.

MPC9600 Data Sheet

LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER

Power Supply Filtering

The MPC9600 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if this

noise is seen on the power supply pins. Random noise on the

instance I/O jitter. The MPC9600 provides separate power

isolate the high switching noise digital outputs from the relatively

sensitive internal analog phase-locked loop. In a digital system

environment where it is more difficult to minimize noise on the

power supplies a second level of isolation may be required. The

simple but effective form of isolation is a power supply filter on the

supply filter scheme. The MPC9600 frequency and phase stability

is most susceptible to noise with spectral content in the 100 kHz

to 20 MHz range. Therefore the filter should be designed to target

this range. The key parameter that needs to be met in the final

filter design is the DC voltage drop across the series filter resistor

the voltage drop criteria.

defined by the required filter characteristics: the RC filter should

provide an attenuation greater than 40 dB for noise whose

spectral content is above 100 kHz. In the example RC filter shown

in Figure 5, the filter cut-off frequency is around 3-5 kHz and the

noise attenuation at 100 kHz is better than 42 dB.

As the noise frequency crosses the series resonant point of an

individual capacitor its overall impedance begins to look inductive

and thus increases with increasing frequency. The parallel

capacitor combination shown ensures that a low impedance path

to ground exists for frequencies well above the bandwidth of the

PLL. Although the MPC9600 has several design features to

minimize the susceptibility to power supply noise (isolated power

and grounds and fully differential PLL) there still may be

applications in which overall performance is being degraded due

to system power supply noise. The power supply filter schemes

discussed in this section should be adequate to eliminate power

supply noise related problems in most designs.

Using the MPC9600 in Zero-Delay Applications

Nested clock trees are typical applications for the MPC9600.

For these applications the MPC9600 offers a differential LVPECL

clock input pair as a PLL reference. This allows for the use of

differential LVPECL primary clock distribution devices such as the

Freescale Semiconductor MC100ES6111 or MC100ES6226,

taking advantage of its superior low-skew performance. Clock

trees using LVPECL for clock distribution and the MPC9600 as

LVCMOS PLL fanout buffer with zero insertion delay will show

significantly lower clock skew than clock distributions developed

from CMOS fanout buffers.

The external feedback option of the MPC9600 PLL allows for

its use as a zero delay buffer. The PLL aligns the feedback clock

output edge with the clock input reference edge and virtually

eliminates the propagation delay through the device.

The remaining insertion delay (skew error) of the MPC9600 in

zero-delay applications is measured between the reference clock

input and any output. This effective delay consists of the static

relative to the feedback output.

Calculation of Part-to-Part Skew

The MPC9600 zero delay buffer supports applications where

critical clock signal timing can be maintained across several

devices. If the reference clock inputs (CCLK or PCLK) of two or

more MPC9600 are connected together, the maximum overall

timing uncertainty from the common CCLK input to any output is:

This maximum timing uncertainty consist of 4 components:

static phase offset, output skew, feedback board trace delay and

I/O (phase) jitter:

Figure 6. MPC9600 Maximum Device-to-Device Skew

MPC9600

10 nF

33...100 nF

Max. skew