MPC9600 REVISION 6 JANUARY 7, 2013

12

©2013 Integrated Device Technology, Inc.

MPC9600 Data Sheet

LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER

Test Reference

Figure 16. Output Duty Cycle (DC)

Figure 18. Cycle-to-Cycle Jitter

Figure 19. Period Jitter

Figure 21. Transition Time Test Reference

The time from the PLL controlled edge to the non controlled edge, divided

by the time between PLL controlled edges, expressed as a percentage

GND

The variation in cycle time of a signal between adjacent cycles, over a random

sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period

over a random sample of cycles

2.4

0.55

GND

PCLK

FB_IN

PCLK

GND

GND

TCLK

FB_IN

The pin-to-pin skew is defined as the worst case difference in propagation delay

between any similar delay path within a single device

GND

GND

CCLK

FB_IN

mean in a random sample of cycles

(PCLK)

Figure 20. I/O Jitter

1.8

0.6