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ICS810001-21 Datasheet(PDF) 3 Page - Integrated Device Technology

Part # ICS810001-21
Description  FemtoClock Dual VCXO Video PLL One LVCMOS/LVTTL clock output
PDF  19 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS810001-21 Datasheet(HTML) 3 Page - Integrated Device Technology

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ICS810001DK-21 REVISION B APRIL 13, 2010
3
©2010 Integrated Device Technology, Inc.
ICS810001-21 Data Sheet
FEMTOCLOCK™ DUAL VCXO VIDEO PLL
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number
Name
Type
Description
1, 2
LF1, LF0
Analog
Input/Output
Loop filter connection node pins.
3
ISET
Analog
Input/Output
Charge pump current setting pin.
4, 11, 25
VDD
Power
Core supply pins.
5, 22
nBP0,
nBP1
Input
Pullup
PLL Bypass control pins. See block diagram.
6, 20, 29
GND
Power
Power supply ground.
7
CLK_SEL
Input
Pulldown
Input clock select. When HIGH selects CLK1. When LOW, selects CLK0.
LVCMOS / LVTTL interface levels.
8, 9
CLK1, CLK0
Input
Pulldown
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
10, 14,
15, 16
V0, V1,
V2, V3
Input
Pulldown
VCXO PLL divider selection pins. LVCMOS/LVTTL interface levels.
12
MR
Input
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the output to go low. When logic LOW, the internal dividers and the
output is enabled. LVCMOS/LVTTL interface levels.
13
MF
Input
Pulldown
FemtoClock multiplication factor select pin. LVCMOS/LVTTL interface levels.
17
VDDA
Power
Analog supply pin.
18
VDDO
Power
Output supply pin.
19
Q
Output
Single-ended VCXO PLL clock output. LVCMOS/LVTTL interface levels.
21
OE
Input
Pullup
Output enable. When logic LOW, the clock output is in high-impedance. When
logic HIGH, the output is enabled. LVCMOS/LVTTL interface levels.
23, 24
N1, N0
Input
Pulldown
FemtoClock output divide select pins. LVCMOS/LVTTL interface levels.
26
XTAL_SEL
Input
Pulldown
Crystal select. When HIGH, selects XTAL1. When LOW, selects XTAL0.
LVCMOS/LVTTL interface levels.
27,
28
XTAL_OUT1,
XTAL_IN1
Input
Crystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output.
30,
31
XTAL_OUT0,
XTAL_IN0
Input
Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output.
32
VDDX
Power
Power supply pin for VCXO charge pump.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4pF
CPD
Power Dissipation Capacitance
(per output)
VDD = VDDO = 3.465V
8.5
pF
RPULLUP
Input Pullup Resistor
51
k
Ω
RPULLDOWN Input Pulldown Resistor
51
k
Ω
ROUT
Output Impedance
22.5
Ω



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