MPC9449 REVISION 6 DECEMBER 21, 2012

3

©2012 Integrated Device Technology, Inc.

MPC9449 Data Sheet

3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER

Table 1. Function Table

Control

Default

0

1

PCLK_SEL

0

LVCMOS clock input selected (CCLK0 or CCLK1)

PCLK differential input selected

CCLK_SEL

0

CCLK0 selected

CCLK1 selected

DSELA, DSELB,

DSELC, DSELD

0 0

0 0

1

2

MR/OE

1

Outputs enabled

Outputs disabled (high impedance)

Table 2. Pin Configuration

Pin

I/O

Type

Function

PCLK, PCLK

Input

LVPECL

Differential LVPECL clock input

CCLK0, CCLK1

Input

LVCMOS

LVCMOS clock inputs

PCLK_SEL

Input

LVCMOS

LVPECL clock input select

CCLK_SEL

Input

LVCMOS

LVCMOS clock input select

DSELA, DSELB, DSELC, DSELD

Input

LVCMOS

Clock divider selection

MR/OE

Input

LVCMOS

Output enable/disable (high-impedance tristate)

QA0-1, QB0-2, QC0-3, QD0-5

Output

LVCMOS

Clock outputs

GND

Supply

Ground

Negative power supply (GND)

Supply

positive power supply for correct operation

Table 3. General Specifications

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Output Termination Voltage

MM

ESD Protection (Machine Model)

200

V

HBM

ESD Protection (Human Body Model)

2000

V

LU

Latch-Up Immunity

200

mA

Power Dissipation Capacitance

12

pF

Per output

Input Capacitance

4.0

pF

Inputs

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated

conditions is not implied.

Symbol

Characteristics

Min

Max

Unit

Condition

Supply Voltage

–0.3

3.8

V

DC Input Voltage

–0.3

V

DC Output Voltage

–0.3

V

DC Input Current

20

mA

DC Output Current

50

mA

Storage Temperature

–65

125

C