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MPC9449 Datasheet(PDF) 5 Page - Integrated Device Technology

Part # MPC9449
Description  3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer High-impedance output control
PDF  11 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

MPC9449 Datasheet(HTML) 5 Page - Integrated Device Technology

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MPC9449 REVISION 6 DECEMBER 21, 2012
5
©2012 Integrated Device Technology, Inc.
MPC9449 Data Sheet
3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER
Table 7. DC Characteristics (VCC = 2.5 V ± 5%, TA = –40C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC  0.3
V
LVCMOS
VIL
Input Low Voltage
–0.3
0.7
V
LVCMOS
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
250
mV
LVPECL
VCMR(1)
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
Common Mode Range
PCLK, PCLK
1.0
VCC–0.6
V
LVPECL
VOH
Output High Voltage
1.8
V
IOH = –15 mA(2)
2. The MPC9449 is capable of driving 50
 transmission lines on the incident edge. Each output drives one 50  parallel terminated
transmission line to a termination voltage of VTT.
VOL
Output Low Voltage
0.6
V
IOL = 15 mA
ZOUT
Output Impedance
17–20
IIN
Input Current(3)
3. Inputs have pull-down or pull-up resistors affecting the input current.
200
AVIN = VCC or GND
ICC
Maximum Quiescent Supply Current
10
mA
All VCC Pins
Table 8. AC Characteristics (VCC = 2.5 V ± 5%, TA = -40C to 85°C)(1)
1. AC characteristics apply for parallel output termination of 50
 to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
400
1000
mV
LVPECL
VCMR(2)
2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay.
Common Mode Range
PCLK, PCLK
1.2
VCC–0.6
V
LVPECL
fmax
Output Frequency
0
200
MHz
fref
Input Frequency
0
200
MHz
tP, REF
Reference Input Pulse Width
1.5
ns
tr, tf
CCLK Input Rise/Fall Time
1.0
ns
0.7 to 1.7 V
tsk(O)
Output-to-Output Skew
Qa outputs
Qb outputs
Qc outputs
Qd outputs
Same Frequency
All outputs
Different Frequencies
All outputs
50
50
50
100
200
300
ps
ps
ps
ps
ps
ps
tsk(PP)
Device-to-Device Skew
5.0
ns
tSK(P)
Output Pulse Skew
350
ps
DCREF = 50%
tPLH, HL
Propagation Delay
CCLK0 or CCLK1 to any Q
PCLK to any Q
1.0
1.0
3.5
3.5
7.0
7.0
ns
ns
tPLZ, HZ
Output Disable Time
OE to any Q
11
ns
tPZL, LZ
Output Enable Time
OE to any Q
11
ns
tr, tf
Output Rise/Fall Time(3)
3. An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition.
0.1
1.0
ns
0.6 to 1.8 V
tJIT(CC)
Cycle-to-Cycle Jitter
RMS (1
)TBD
ps



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