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EP3SE110 Datasheet(PDF) 189 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 189 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–179
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
1.5-V HSTL
CLASS I
GCLK
t
su
-1.141
-1.232
-1.824
-1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377
ns
t
h
1.267
1.371
2.038
2.044
2.195
2.117
2.564
2.062
2.214
2.147
2.611
ns
GCLK
PLL
t
su
0.937
1.021
1.778
1.804
2.104
1.990
1.814
1.790
2.127
2.005
1.863
ns
t
h
-0.672
-0.735
-1.323
-1.336 -1.580 -1.496 -1.313 -1.312 -1.591 -1.499 -1.355
ns
1.5-V HSTL
CLASS II
GCLK
t
su
-1.141
-1.232
-1.824
-1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377
ns
t
h
1.267
1.371
2.038
2.044
2.195
2.117
2.564
2.062
2.214
2.147
2.611
ns
GCLK
PLL
t
su
0.937
1.021
1.778
1.804
2.104
1.990
1.814
1.790
2.127
2.005
1.863
ns
t
h
-0.672
-0.735
-1.323
-1.336 -1.580 -1.496 -1.313 -1.312 -1.591 -1.499 -1.355
ns
1.2-V HSTL
CLASS I
GCLK
t
su
-1.132
-1.220
-1.815
-1.815 -1.938 -1.871 -2.317 -1.824 -1.948 -1.892 -2.361
ns
t
h
1.258
1.359
2.029
2.034
2.179
2.101
2.548
2.053
2.198
2.131
2.595
ns
GCLK
PLL
t
su
0.946
1.033
1.787
1.814
2.120
2.006
1.830
1.799
2.143
2.021
1.879
ns
t
h
-0.681
-0.747
-1.332
-1.346 -1.596 -1.512 -1.329 -1.321 -1.607 -1.515 -1.371
ns
1.2-V HSTL
CLASS II
GCLK
t
su
-1.132
-1.220
-1.815
-1.815 -1.938 -1.871 -2.317 -1.824 -1.948 -1.892 -2.361
ns
t
h
1.258
1.359
2.029
2.034
2.179
2.101
2.548
2.053
2.198
2.131
2.595
ns
GCLK
PLL
t
su
0.946
1.033
1.787
1.814
2.120
2.006
1.830
1.799
2.143
2.021
1.879
ns
t
h
-0.681
-0.747
-1.332
-1.346 -1.596 -1.512 -1.329 -1.321 -1.607 -1.515 -1.371
ns
3.0-V PCI
GCLK
t
su
-1.245
-1.307
-1.922
-1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527
ns
t
h
1.368
1.446
2.134
2.178
2.445
2.369
2.825
2.204
2.461
2.387
2.768
ns
GCLK
PLL
t
su
0.873
0.934
1.673
1.686
1.783
1.677
1.686
1.690
1.802
1.690
1.741
ns
t
h
-0.609
-0.649
-1.219
-1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226
ns
3.0-V
PCI-X
GCLK
t
su
-1.245
-1.307
-1.922
-1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527
ns
t
h
1.368
1.446
2.134
2.178
2.445
2.369
2.825
2.204
2.461
2.387
2.768
ns
GCLK
PLL
t
su
0.873
0.934
1.673
1.686
1.783
1.677
1.686
1.690
1.802
1.690
1.741
ns
t
h
-0.609
-0.649
-1.219
-1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226
ns
Table 1–92. EP3SL340 Row Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V



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