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EP3SE110 Datasheet(PDF) 239 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 239 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–229
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
EP3SE80 I/O Timing Parameters
Table 1–111 through Table 1–114 list the maximum I/O timing parameters for
EP3SE80 devices for single-ended I/O standards.
Table 1–111 lists the EP3SE80 column pins input timing parameters for single-ended
I/O standards.
Table 1–111. EP3SE80 Column Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V LVTTL
GCLK
t
su
-1.054
-1.054
-1.505 -1.636 -1.872 -1.819 -2.173 -1.636 -1.872 -1.819 -2.173
ns
t
h
1.195
1.195
1.704
1.861
2.117
2.050
2.409
1.861
2.117
2.050
2.409
ns
GCLK
PLL
t
su
-1.307
-1.307
-1.870 -2.028 -2.321 -2.214 -2.661 -2.028 -2.321 -2.214 -2.661
ns
t
h
1.605
1.605
2.302
2.513
2.858
2.721
3.186
2.513
2.858
2.721
3.186
ns
3.3-V
LVCMOS
GCLK
t
su
-1.054
-1.054
-1.505 -1.636 -1.872 -1.819 -2.173 -1.636 -1.872 -1.819 -2.173
ns
t
h
1.195
1.195
1.704
1.861
2.117
2.050
2.409
1.861
2.117
2.050
2.409
ns
GCLK
PLL
t
su
-1.307
-1.307
-1.870 -2.028 -2.321 -2.214 -2.661 -2.028 -2.321 -2.214 -2.661
ns
t
h
1.605
1.605
2.302
2.513
2.858
2.721
3.186
2.513
2.858
2.721
3.186
ns
3.0-V LVTTL
GCLK
t
su
-1.065
-1.065
-1.504 -1.638 -1.871 -1.818 -2.172 -1.638 -1.871 -1.818 -2.172
ns
t
h
1.206
1.206
1.703
1.863
2.116
2.049
2.408
1.863
2.116
2.049
2.408
ns
GCLK
PLL
t
su
-1.318
-1.318
-1.869 -2.030 -2.320 -2.213 -2.660 -2.030 -2.320 -2.213 -2.660
ns
t
h
1.616
1.616
2.301
2.515
2.857
2.720
3.185
2.515
2.857
2.720
3.185
ns
3.0-V
LVCMOS
GCLK
t
su
-1.065
-1.065
-1.504 -1.638 -1.871 -1.818 -2.172 -1.638 -1.871 -1.818 -2.172
ns
t
h
1.206
1.206
1.703
1.863
2.116
2.049
2.408
1.863
2.116
2.049
2.408
ns
GCLK
PLL
t
su
-1.318
-1.318
-1.869 -2.030 -2.320 -2.213 -2.660 -2.030 -2.320 -2.213 -2.660
ns
t
h
1.616
1.616
2.301
2.515
2.857
2.720
3.185
2.515
2.857
2.720
3.185
ns
2.5 V
GCLK
t
su
-1.060
-1.060
-1.513 -1.650 -1.890 -1.837 -2.191 -1.650 -1.890 -1.837 -2.191
ns
t
h
1.201
1.201
1.712
1.875
2.135
2.068
2.427
1.875
2.135
2.068
2.427
ns
GCLK
PLL
t
su
-1.313
-1.313
-1.878 -2.042 -2.339 -2.232 -2.679 -2.042 -2.339 -2.232 -2.679
ns
t
h
1.611
1.611
2.310
2.527
2.876
2.739
3.204
2.527
2.876
2.739
3.204
ns
1.8 V
GCLK
t
su
-1.082
-1.082
-1.553 -1.686 -1.888 -1.835 -2.189 -1.686 -1.888 -1.835 -2.189
ns
t
h
1.225
1.225
1.752
1.911
2.133
2.066
2.425
1.911
2.133
2.066
2.425
ns
GCLK
PLL
t
su
-1.335
-1.335
-1.918 -2.078 -2.337 -2.230 -2.677 -2.078 -2.337 -2.230 -2.677
ns
t
h
1.635
1.635
2.350
2.563
2.874
2.737
3.202
2.563
2.874
2.737
3.202
ns
1.5 V
GCLK
t
su
-1.072
-1.072
-1.530 -1.654 -1.818 -1.765 -2.119 -1.654 -1.818 -1.765 -2.119
ns
t
h
1.215
1.215
1.729
1.879
2.063
1.996
2.355
1.879
2.063
1.996
2.355
ns
GCLK
PLL
t
su
-1.325
-1.325
-1.895 -2.046 -2.267 -2.160 -2.607 -2.046 -2.267 -2.160 -2.607
ns
t
h
1.625
1.625
2.327
2.531
2.804
2.667
3.132
2.531
2.804
2.667
3.132
ns
1.2 V
GCLK
t
su
-1.020
-1.020
-1.453 -1.555 -1.662 -1.609 -1.963 -1.555 -1.662 -1.609 -1.963
ns
t
h
1.163
1.163
1.652
1.780
1.907
1.840
2.199
1.780
1.907
1.840
2.199
ns
GCLK
PLL
t
su
-1.273
-1.273
-1.818 -1.947 -2.111 -2.004 -2.451 -1.947 -2.111 -2.004 -2.451
ns
t
h
1.573
1.573
2.250
2.432
2.648
2.511
2.976
2.432
2.648
2.511
2.976
ns



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