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EP3SE110 Datasheet(PDF) 243 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 243 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–233
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
SSTL-15
CLASS I
GCLK
t
su
-0.863
-0.916
-1.285 -1.385 -1.491 -1.438 -1.659 -1.390 -1.495 -1.446 -1.703
ns
t
h
0.987
1.056
1.483
1.605
1.732
1.668
1.893
1.620
1.745
1.685
1.938
ns
GCLK
PLL
t
su
1.084
1.095
1.762
1.994
2.219
2.105
2.032
2.007
2.231
2.115
2.078
ns
t
h
-0.824
-0.816
-1.347 -1.531 -1.706 -1.618 -1.537 -1.534 -1.708 -1.619 -1.581
ns
1.8-V HSTL
CLASS I
GCLK
t
su
-0.877
-0.928
-1.300 -1.395 -1.509 -1.456 -1.677 -1.401 -1.512 -1.463 -1.720
ns
t
h
1.001
1.068
1.497
1.615
1.750
1.686
1.911
1.631
1.762
1.702
1.955
ns
GCLK
PLL
t
su
1.070
1.083
1.747
1.984
2.201
2.087
2.014
1.996
2.214
2.098
2.061
ns
t
h
-0.810
-0.804
-1.333 -1.521 -1.688 -1.600 -1.519 -1.523 -1.691 -1.602 -1.564
ns
1.8-V HSTL
CLASS II
GCLK
t
su
-0.877
-0.928
-1.300 -1.395 -1.509 -1.456 -1.677 -1.401 -1.512 -1.463 -1.720
ns
t
h
1.001
1.068
1.497
1.615
1.750
1.686
1.911
1.631
1.762
1.702
1.955
ns
GCLK
PLL
t
su
1.070
1.083
1.747
1.984
2.201
2.087
2.014
1.996
2.214
2.098
2.061
ns
t
h
-0.810
-0.804
-1.333 -1.521 -1.688 -1.600 -1.519 -1.523 -1.691 -1.602 -1.564
ns
1.5-V HSTL
CLASS I
GCLK
t
su
-0.863
-0.916
-1.285 -1.385 -1.491 -1.438 -1.659 -1.390 -1.495 -1.446 -1.703
ns
t
h
0.987
1.056
1.483
1.605
1.732
1.668
1.893
1.620
1.745
1.685
1.938
ns
GCLK
PLL
t
su
1.084
1.095
1.762
1.994
2.219
2.105
2.032
2.007
2.231
2.115
2.078
ns
t
h
-0.824
-0.816
-1.347 -1.531 -1.706 -1.618 -1.537 -1.534 -1.708 -1.619 -1.581
ns
1.5-V HSTL
CLASS II
GCLK
t
su
-0.863
-0.916
-1.285 -1.385 -1.491 -1.438 -1.659 -1.390 -1.495 -1.446 -1.703
ns
t
h
0.987
1.056
1.483
1.605
1.732
1.668
1.893
1.620
1.745
1.685
1.938
ns
GCLK
PLL
t
su
1.084
1.095
1.762
1.994
2.219
2.105
2.032
2.007
2.231
2.115
2.078
ns
t
h
-0.824
-0.816
-1.347 -1.531 -1.706 -1.618 -1.537 -1.534 -1.708 -1.619 -1.581
ns
1.2-V HSTL
CLASS I
GCLK
t
su
-0.854
-0.904
-1.276 -1.375 -1.475 -1.422 -1.643 -1.381 -1.479 -1.430 -1.687
ns
t
h
0.978
1.044
1.474
1.595
1.716
1.652
1.877
1.611
1.729
1.669
1.922
ns
GCLK
PLL
t
su
1.093
1.107
1.771
2.004
2.235
2.121
2.048
2.016
2.247
2.131
2.094
ns
t
h
-0.833
-0.828
-1.356 -1.541 -1.722 -1.634 -1.553 -1.543 -1.724 -1.635 -1.597
ns
1.2-V HSTL
CLASS II
GCLK
t
su
-0.854
-0.904
-1.276 -1.375 -1.475 -1.422 -1.643 -1.381 -1.479 -1.430 -1.687
ns
t
h
0.978
1.044
1.474
1.595
1.716
1.652
1.877
1.611
1.729
1.669
1.922
ns
GCLK
PLL
t
su
1.093
1.107
1.771
2.004
2.235
2.121
2.048
2.016
2.247
2.131
2.094
ns
t
h
-0.833
-0.828
-1.356 -1.541 -1.722 -1.634 -1.553 -1.543 -1.724 -1.635 -1.597
ns
3.0-V PCI
GCLK
t
su
-0.928
-0.975
-1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934
ns
t
h
1.051
1.114
1.563
1.704
1.845
1.881
2.131
1.724
1.955
1.895
2.173
ns
GCLK
PLL
t
su
1.081
1.099
1.773
1.999
1.982
2.001
1.796
2.013
1.998
2.019
1.845
ns
t
h
-0.819
-0.819
-1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344
ns
3.0-V
PCI-X
GCLK
t
su
-0.928
-0.975
-1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934
ns
t
h
1.051
1.114
1.563
1.704
1.845
1.881
2.131
1.724
1.955
1.895
2.173
ns
GCLK
PLL
t
su
1.081
1.099
1.773
1.999
1.982
2.001
1.796
2.013
1.998
2.019
1.845
ns
t
h
-0.819
-0.819
-1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344
ns
Table 1–112. EP3SE80 Row Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V



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