PIC16LF1824 datasheet(246/440 Pages) MICROCHIP

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PIC16(L)F1847

DS40001453D-page 246

Preliminary

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25.4.9

ACKNOWLEDGE SEQUENCE

The ninth SCLx pulse for any transferred byte in I2C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDAx line low. The transmitter must release

control of the line during this time to shift in the

response. The Acknowledge (ACK) is an active-low

signal, pulling the SDAx line low indicated to the trans-

mitter that the device has received the transmitted

data and is ready to receive more.

The result of an ACK is placed in the ACKSTAT bit of

the SSPxCON2 register.

Slave software, when the AHEN and DHEN bits are

set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit of the SSPxCON2

Slave hardware will generate an ACK response if the

AHEN and DHEN bits of the SSPxCON3 register are

clear.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSPxSTAT regis-

ter or the SSPOV bit of the SSPxCON1 register are

set when a byte is received.

When the module is addressed, after the 8th falling

edge of SCLx on the bus, the ACKTIM bit of the

SSPxCON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN

bit is enabled.

25.5

I2C

SLAVE MODE OPERATION

The MSSPx Slave mode operates in one of four

modes selected in the SSPM bits of SSPxCON1 regis-

ter. The modes can be divided into 7-bit and 10-bit

Addressing mode. 10-bit Addressing modes operate

the same as 7-bit with some additional overhead for

handling the larger addresses.

Modes with Start and Stop bit interrupts operate the

same as the other modes with SSPxIF additionally

getting set upon detection of a Start, Restart, or Stop

condition.

25.5.1

SLAVE MODE ADDRESSES

The SSPxADD register (Register 25-6) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSPxBUF register and an

interrupt is generated. If the value does not match, the

module goes idle and no indication is given to the soft-

ware that anything happened.

The SSPx Mask register (Register 25-5) affects the

address matching process. See Section 25.5.9

“SSPx Mask Register” for more information.

25.5.1.1

I2C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

25.5.1.2

I2C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9

and A8 are the two MSb’s of the 10-bit address and

stored in bits 2 and 1 of the SSPxADD register.

After the acknowledge of the high byte the UA bit is set

and SCLx is held low until the user updates SSPxADD

with the low address. The low address byte is clocked

in and all eight bits are compared to the low address

value in SSPxADD. Even if there is not an address

match; SSPxIF and UA are set, and SCLx is held low

until SSPxADD is updated to receive a high byte

again. When SSPxADD is updated the UA bit is

cleared. This ensures the module is ready to receive

the high address byte on the next communication.

A high and low address match as a write request is

required at the start of all 10-bit addressing communi-

cation. A transmission can be initiated by issuing a

Restart once the slave is addressed, and clocking in

the high address with the R/W bit set. The slave hard-

ware will then acknowledge the read request and

prepare to clock out data. This is only valid for a slave

after it has received a complete high and low address

byte match.

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