 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PIC16LF1824 Datasheet(PDF) 96 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC16LF1824 Datasheet(HTML) 96 Page - Microchip Technology |
|
|
96 / 440 page  PIC16(L)F1847 DS40001453D-page 96 Preliminary 2011-2013 Microchip Technology Inc. TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS REGISTER 8-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 — — — — — — BCL2IF SSP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware bit 7-2 Unimplemented: Read as ‘0’ bit 1 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = A Bus Collision was detected (must be cleared in software) 0 = No Bus collision was detected bit 0 SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit 1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software) 0 = Waiting to Transmit/Receive/Bus Condition in progress Note 1: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 88 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 175 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 89 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 90 PIE3 — — CCP4IE CCP3IE TMR6IE —TMR4IE — 91 PIE4 — — — — — — BCL2IE SSP2IE 92 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 93 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF 94 PIR3 — — CCP4IF CCP3IF TMR6IF —TMR4IF — 95 PIR4 — — — — — — BCL2IF SSP2IF 96 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupts. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
