PIC16LF1824 datasheet(95/440 Pages) MICROCHIP

95 / 440 page

 2011-2013 Microchip Technology Inc.

Preliminary

DS40001453D-page 95

PIC16(L)F1847

PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

U-0

R/W-0/0

U-0

R/W-0/0

U-0

—

CCP4IF

CCP3IF

TMR6IF

—TMR4IF

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-6

Unimplemented: Read as ‘0’

bit 5

CCP4IF: CCP4 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 4

CCP3IF: CCP3 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 3

TMR6IF: TMR6 to PR6 Match Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 2

Unimplemented: Read as ‘0’

bit 1

TMR4IF: TMR4 to PR4 Match Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 0

Unimplemented: Read as ‘0’

Note 1: Interrupt flag bits are set when an inter-

rupt condition occurs, regardless of the

state of its corresponding enable bit or

the Global Enable bit, GIE of the INTCON

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

PIC16LF1824 Datasheet(PDF) 95 Page - Microchip Technology

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