PIC16LF1824 datasheet(49/440 Pages) MICROCHIP

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Preliminary

DS40001453D-page 49

PIC16(L)F1847

4.3

Code Protection

Code protection allows the device to be protected from

unauthorized access. Program memory protection and

data EEPROM protection are controlled independently.

Internal access to the program memory and data

EEPROM are unaffected by any code protection

setting.

4.3.1

PROGRAM MEMORY PROTECTION

The entire program memory space is protected from

external reads and writes by the CP bit in Configuration

Words. When CP = 0, external reads and writes of

program memory are inhibited and a read will return all

‘0’s. The CPU can continue to read program memory,

regardless of the protection bit settings. Writing the

program memory is dependent upon the write

protection

setting.

See

Section 4.4

“Write

Protection” for more information.

4.3.2

DATA EEPROM PROTECTION

The entire data EEPROM is protected from external

reads and writes by the CPD bit. When CPD = 0, exter-

nal reads and writes of data EEPROM are inhibited.

The CPU can continue to read and write data EEPROM

regardless of the protection bit settings.

4.4

Write Protection

Write protection allows the device to be protected from

unintended self-writes. Applications, such as boot-

loader software, can be protected while allowing other

regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the

size of the program memory block that is protected.

4.5

User ID

Four memory locations (8000h-8003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

readable and writable during normal execution. See

Section 11.5 “User ID, Device ID and Configuration

Word Access” for more information on accessing these

memory locations. For more information on checksum

calculation, see the “PIC16(L)F1847/PIC12(L)F1840

Memory Programming Specification” (DS41439).

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