PIC16LF1824 datasheet(261/440 Pages) MICROCHIP

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Preliminary

DS40001453D-page 261

PIC16(L)F1847

FIGURE 25-23:

CLOCK SYNCHRONIZATION TIMING

25.5.8

GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I2C bus is such that

the first byte after the Start condition usually deter-

mines which device will be the slave addressed by the

master device. The exception is the general call

address which can address all devices. When this

address is used, all devices should, in theory, respond

with an acknowledge.

The general call address is a reserved address in the

I2C protocol, defined as address 0x00. When the

GCEN bit of the SSPxCON2 register is set, the slave

module will automatically ACK the reception of this

address regardless of the value stored in SSPxADD.

After the slave clocks in an address of all zeros with

the R/W bit clear, an interrupt is generated and slave

software

can

read

SSPxBUF

and

respond.

Figure 25-24

shows

general

call

reception

sequence.

In 10-bit Address mode, the UA bit will not be set on

the reception of the general call address. The slave

will prepare to receive the second byte as data, just as

it would in 7-bit mode.

If the AHEN bit of the SSPxCON3 register is set, just

as with any other address reception, the slave

hardware will stretch the clock after the 8th falling

edge of SCLx. The slave must then set its ACKDT

value and release the clock with communication

progressing as it would normally.

SDAx

SCLx

DX ‚

– 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPxCON1

CKP

Master device

releases clock

Master device

asserts clock

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