 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PIC16LF1824 Datasheet(PDF) 314 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC16LF1824 Datasheet(HTML) 314 Page - Microchip Technology |
|
|
314 / 440 page  PIC16(L)F1847 DS40001453D-page 314 Preliminary 2011-2013 Microchip Technology Inc. 26.4.2.3 EUSART Synchronous Slave Reception The operation of the Synchronous Master and Slave modes is identical (Section 26.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 26.4.2.4 Synchronous Slave Reception Setup: 1. Set the SYNC and SPEN bits and clear the CSRC bit. 2. Clear the ANSEL bit for both the CK and DT pins (if applicable). 3. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 4. If 9-bit reception is desired, set the RX9 bit. 5. Set the CREN bit to enable reception. 6. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. 7. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 26-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL 118 APFCON1 — — — — — — — TXCKSEL 118 BAUDCON ABDOVF RCIDL —SCKP BRG16 — WUE ABDEN 298 INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 88 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 89 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 93 RCREG EUSART Receive Data Register 292* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 297 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 126 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 296 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. * Page provides register information. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
