PIC16LF1824 datasheet(365/440 Pages) MICROCHIP

365 / 440 page

 2011-2013 Microchip Technology Inc.

Preliminary

DS40001453D-page 365

PIC16(L)F1847

TABLE 30-8:

ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS (NOTE 1, 2, 3)

TABLE 30-9:

ADC CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

Tested at 25°C

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

AD01

Resolution

—

bit

AD02

EIL

Integral Error

—

±1

±1.7

LSb VREF = 3.0V

AD03

EDL

Differential Error

—

±1

—

LSb No missing codes

VREF = 3.0V

AD04

EOFF Offset Error

—

±1

±2.5

LSb VREF = 3.0V

AD05

EGN

Gain Error

—

±1

±2.0

LSb VREF = 3.0V

AD06

VREF Reference Voltage (Note 4)

1.8

—

VDD

VVREF = (VREF+ minus VREF-)

AD07

VAIN

Full-Scale Range

VSS

—VREF

AD08

ZAIN

Recommended Impedance of

Analog Voltage Source

——

 Can go higher if external 0.01F capacitor is

present on input pin.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:

Total Absolute Error includes integral, differential, offset and gain errors.

The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.

ADC VREF is from external VREF, VDD or FVR, whichever is selected as reference input.

ADC Reference Voltage (Ref+) is the selected reference input, VREF+ pin, VDD pin or the FVR selected as the reference

input, the FVR Buffer1 output selection must be 2.048V or 4.096V (ADFVR<1:0> = 1x).

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C

 TA  +125°C

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

AD130* TAD

ADC Clock Period

1.0

—

9.0

sFOSC-based

ADC Internal RC Oscillator

Period

1.0

2.5

6.0

s

ADCS<1:0> = 11

(FRC Oscillator mode)

AD131

TCNV

Conversion Time (not

including Acquisition Time)

(Note 1)

—11

—

TAD

Set GO/DONE bit to conversion

complete

AD132* TACQ

Acquisition Time

—

5.0

—

s

AD133* THCD

Holding Capacitor Disconnect

—

0.5*TAD + 40 ns

(0.5*TAD + 40 ns)

(1.5*TAD + 40 ns)

—

ADCS<2:0>

 x11 (FOSC-based)

ADCS<2:0>

 x11 (ADC FRC mode)

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:

The ADRES register may be read on the following TCY cycle.

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