PIC16LF1824 datasheet(373/440 Pages) MICROCHIP

373 / 440 page

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Preliminary

DS40001453D-page 373

PIC16(L)F1847

FIGURE 30-21:

I2C™ BUS DATA TIMING

TABLE 30-16: I2C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min.

Max.

Units

Conditions

SP100*

THIGH

Clock high time

100 kHz mode

4.0

—

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

s

Device must operate at a

minimum of 10 MHz

SSP module

1.5TCY

——

SP101*

TLOW

Clock low time

100 kHz mode

4.7

—

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

s

Device must operate at a

minimum of 10 MHz

SSP module

1.5TCY

——

SP102*

SDA and SCL

rise time

100 kHz mode

—

1000

400 kHz mode

20 + 0.1CB

300

CB is specified to be from

10-400 pF

SP103*

SDA and SCL fall time 100 kHz mode

—

250

400 kHz mode

20 + 0.1CB

250

CB is specified to be from

10-400 pF

SP106*

THD:DAT

Data input hold time

100 kHz mode

—

400 kHz mode

0.9

s

SP107*

TSU:DAT

Data input setup time 100 kHz mode

250

—

(Note 2)

400 kHz mode

100

—

SP109*

TAA

Output valid from

clock

100 kHz mode

—

3500

(Note 1)

400 kHz mode

—

SP110*

TBUF

Bus free time

100 kHz mode

4.7

—

s

Time the bus must be free

before a new transmission

can start

400 kHz mode

1.3

—

s

SP111

Bus capacitive loading

—

400

These parameters are characterized but not tested.

Note 1:

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)

of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the require-

ment TSU:DAT

250 ns must then be met. This will automatically be the case if the device does not stretch the low

period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit

to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification),

before the SCL line is released.

Note:

Refer to Figure 30-5 for load conditions.

SP90

SP91

SP92

SP100

SP101

SP103

SP106

SP107

SP109

SP110

SP102

SCLx

SDAx

Out

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