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PIC16LF1824 Datasheet(PDF) 434 Page - Microchip Technology |
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PIC16LF1824 Datasheet(HTML) 434 Page - Microchip Technology |
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434 / 440 page  PIC16(L)F1847 DS40001453D-page 434 Preliminary 2011-2013 Microchip Technology Inc. Prescaler................................................................... 179 Specifications............................................................ 364 Timer1 Gate Selecting Source............................................... 179 TMR1H Register ....................................................... 177 TMR1L Register........................................................ 177 Timer2 Associated registers.................................................. 192 Timer2/4/6 ......................................................................... 189 Associated registers.................................................. 192 Timers Timer1 T1CON.............................................................. 185 T1GCON ........................................................... 186 Timer2/4/6 TXCON ............................................................. 191 Timing Diagrams Acknowledge Sequence ........................................... 271 ADC Conversion ....................................................... 366 ADC Conversion (Sleep Mode)................................. 366 Asynchronous Reception .......................................... 294 Asynchronous Transmission..................................... 290 Asynchronous Transmission (Back to Back) ............ 291 Auto Wake-up Bit (WUE) During Normal Operation . 306 Auto Wake-up Bit (WUE) During Sleep .................... 306 Automatic Baud Rate Calibration .............................. 304 Baud Rate Generator with Clock Arbitration ............. 264 BRG Reset Due to SDA Arbitration During Start Condition........................................................... 275 Brown-out Reset (BOR) ............................................ 362 Brown-out Reset Situations ........................................ 75 Bus Collision During a Repeated Start Condition (Case 1) ............................................................ 276 Bus Collision During a Repeated Start Condition (Case 2) ............................................................ 277 Bus Collision During a Start Condition (SCL = 0) ..... 275 Bus Collision During a Stop Condition (Case 1) ....... 278 Bus Collision During a Stop Condition (Case 2) ....... 278 Bus Collision During Start Condition (SDA only) ...... 274 Bus Collision for Transmit and Acknowledge............ 273 CLKOUT and I/O....................................................... 361 Clock Synchronization .............................................. 261 Clock Timing ............................................................. 359 Comparator Output ................................................... 163 Enhanced Capture/Compare/PWM (ECCP) ............. 364 Fail-Safe Clock Monitor (FSCM) ................................. 64 First Start Bit Timing ................................................. 265 Full-Bridge PWM Output ........................................... 217 Half-Bridge PWM Output .................................. 215, 222 I2C Bus Data ............................................................. 373 I2C Bus Start/Stop Bits.............................................. 372 I2C Master Mode (7 or 10-Bit Transmission) ............ 268 I2C Master Mode (7-Bit Reception)........................... 270 I2C Stop Condition Receive or Transmit Mode ......... 272 INT Pin Interrupt.......................................................... 86 Internal Oscillator Switch Timing................................. 59 PWM Auto-shutdown ................................................ 221 Firmware Restart .............................................. 220 PWM Direction Change ............................................ 218 PWM Direction Change at Near 100% Duty Cycle ... 219 PWM Output (Active-High)........................................ 213 PWM Output (Active-Low) ........................................ 214 Repeat Start Condition.............................................. 266 Reset Start-up Sequence............................................ 78 Reset, WDT, OST and Power-up Timer ................... 362 Send Break Character Sequence............................. 307 SPI Master Mode (CKE = 1, SMP = 1) ..................... 369 SPI Mode (Master Mode).......................................... 237 SPI Slave Mode (CKE = 0) ....................................... 370 SPI Slave Mode (CKE = 1) ....................................... 370 Synchronous Reception (Master Mode, SREN) ....... 312 Synchronous Transmission ...................................... 309 Synchronous Transmission (Through TXEN) ........... 309 Timer0 and Timer1 External Clock ........................... 363 Timer1 Incrementing Edge ....................................... 181 Two Speed Start-up.................................................... 62 USART Synchronous Receive (Master/Slave) ......... 368 USART Synchronous Transmission (Master/Slave). 368 Wake-up from Interrupt............................................... 98 Timing Diagrams and Specifications PLL Clock ................................................................. 360 Timing Parameter Symbology .......................................... 358 Timing Requirements I2C Bus Data............................................................. 373 SPI Mode .................................................................. 371 TMR0 Register.................................................................... 27 TMR1H Register ................................................................. 27 TMR1L Register.................................................................. 27 TMR2 Register.............................................................. 27, 35 TRIS.................................................................................. 344 TRISA Register........................................................... 28, 120 TRISB ............................................................................... 125 TRISB Register........................................................... 28, 126 Two-Speed Clock Start-up Mode........................................ 61 TXCON (Timer2/4/6) Register .......................................... 191 TxCON Register ............................................................... 211 TXREG ............................................................................. 289 TXREG Register ................................................................. 30 TXSTA Register.................................................................. 30 BRGH Bit .................................................................. 299 U USART Synchronous Master Mode Requirements, Synchronous Receive .............. 368 Requirements, Synchronous Transmission...... 368 Timing Diagram, Synchronous Receive ........... 368 Timing Diagram, Synchronous Transmission... 368 V VREF. SEE ADC Reference Voltage W Wake-up on Break ............................................................ 305 Wake-up Using Interrupts ................................................... 98 Watchdog Timer (WDT)...................................................... 77 Modes....................................................................... 100 Specifications ........................................................... 363 WCOL ....................................................... 264, 267, 269, 271 WCOL Status Flag.................................... 264, 267, 269, 271 WDTCON Register ........................................................... 101 WPUB Register......................................................... 121, 127 Write Protection .................................................................. 49 WWW Address ................................................................. 435 WWW, On-Line Support ................................................... 2, 7 |
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