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AD5272 Datasheet(PDF) 7 Page - Analog Devices |
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AD5272 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 28 page  Data Sheet AD5272/AD5274 Rev. D | Page 7 of 28 INTERFACE TIMING SPECIFICATIONS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7. Limit at TMIN, TMAX Parameter Conditions1 Min Max Unit Description fSCL2 Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz Serial clock frequency t1 Standard mode 4 µs tHIGH, SCL high time Fast mode 0.6 µs tHIGH, SCL high time t2 Standard mode 4.7 µs tLOW, SCL low time Fast mode 1.3 µs tLOW, SCL low time t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns tSU;DAT, data setup time t4 Standard mode 0 3.45 µs tHD;DAT, data hold time Fast mode 0 0.9 µs tHD;DAT, data hold time t5 Standard mode 4.7 µs tSU;STA, set-up time for a repeated start condition Fast mode 0.6 µs tSU;STA, set-up time for a repeated start condition t6 Standard mode 4 µs tHD;STA, hold time (repeated) start condition Fast mode 0.6 µs tHD;STA, hold time (repeated) start condition High speed mode 160 ns tHD;STA, hold time (repeated) start condition t7 Standard mode 4.7 µs tBUF, bus free time between a stop and a start condition Fast mode 1.3 µs tBUF, bus free time between a stop and a start condition t8 Standard mode 4 µs tSU;STO, setup time for a stop condition Fast mode 0.6 µs tSU;STO, setup time for a stop condition t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 300 ns tRDA, rise time of SDA signal t10 Standard mode 300 ns tFDA, fall time of SDA signal Fast mode 300 ns tFDA, fall time of SDA signal t11 Standard mode 1000 ns tRCL, rise time of SCL signal Fast mode 300 ns tRCL, rise time of SCL signal t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit Fast mode 300 ns tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit t12 Standard mode 300 ns tFCL, fall time of SCL signal Fast mode 300 ns tFCL, fall time of SCL signal t13 RESET pulse time 20 ns Minimum RESET low time tSP3 Fast mode 0 50 ns Pulse width of spike suppressed tEXEC4, 5 500 ns Command execute time tRDAC_R-PERF 2 µs RDAC register write command execute time (R-Perf mode) tRDAC_NORMAL 600 ns RDAC register write command execute time (normal mode) tMEMORY_READ 6 µs Memory readback execute time tMEMORY_PROGRAM 350 ms Memory program time tRESET 600 µs Reset 50-TP restore time t POWER-UP 6 2 ms Power-on 50-TP restore time 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode. 4 Refer to tRDAC_R-PERF and tRDAC_NORMAL for RDAC register write operations. 5 Refer to t MEMORY_READ and tMEMORY_PROGRAM for memory commands operations. 6 Maximum time after VDD − VSS is equal to 2.5 V. |
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