AD5272 datasheet(24/28 Pages) AD

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AD5272/AD5274

Data Sheet

Rev. D | Page 24 of 28

EXT_CAP CAPACITOR

A 1 μF capacitor to VSS must be connected to the EXT_CAP pin

(see Figure 47) on power-up and throughout the operation of

the AD5272/AD5274.

AD5272/

AD5274

50_OTP

MEMORY

BLOCK

EXT_CAP

1µF

VSS

Figure 47. EXT_CAP Hardware Setup

TERMINAL VOLTAGE OPERATING RANGE

The positive VDD and negative VSS power supplies of the

AD5272/AD5274 define the boundary conditions for proper

2-terminal digital resistor operation. Supply signals present on

Terminal A and Terminal W that exceed VDD or VSS are clamped

by the internal forward-biased diodes (see Figure 48).

VSS

VDD

Figure 48. Maximum Terminal Voltages Set by VDD and VSS

The ground pins of the AD5272/AD5274 devices are primarily

used as digital ground references. To minimize the digital

ground bounce, join the AD5272/AD5274 ground terminal

remotely to the common ground. The digital input control

signals to the AD5272/AD5274 must be referenced to the

device ground pin (GND) and satisfy the logic level defined in

the Specifications section. An internal level shift circuit ensures

that the common-mode voltage range of the three terminals

extends from VSS to VDD, regardless of the digital input level.

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at

Terminal A and Terminal W (see Figure 48), it is important to

power VDD/VSS first before applying any voltage to Terminal A

and Terminal W; otherwise, the diode is forward-biased such

that VDD/VSS are powered unintentionally. The ideal power-up

sequence is VSS, GND, VDD, digital inputs, VA, and VW. The

order of powering VA, VW, and digital inputs is not important

as long as they are powered after VDD/VSS.

As soon as VDD is powered, the power-on preset activates, which

first sets the RDAC to midscale and then restores the last

programmed 50-TP value to the RDAC register.

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