AD7265BCP datasheet(22/28 Pages) AD

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AD7265

Rev. A | Page 22 of 28

SERIAL INTERFACE

A minimum of 14 serial clock cycles are required to perform

the conversion process and to access data from one conversion

on either data line of the AD7265.

Figure 41 shows the detailed timing diagram for serial inter-

facing to the AD7265. The serial clock provides the conversion

clock and controls the transfer of information from the AD7265

during conversion.

CS going low provides the

leading zero to be read in by the microcontroller or DSP. The

remaining data is then clocked out by subsequent SCLK falling

edges, beginning with a second leading zero. Therefore, the first

falling clock edge on the serial clock has the leading zero pro-

vided and also clocks out the second leading zero. The 12-bit

result then follows with the final bit in the data transfer valid on

the 14

The

signal initiates the data transfer and conversion process.

The falling edge of CS puts the track-and-hold into hold mode,

at which point the analog input is sampled and the bus is taken

out of three-state. The conversion is also initiated at this point

and requires a minimum of 14 SCLKs to complete. Once 13

SCLK falling edges have elapsed, the track-and-hold goes back

into track on the next SCLK rising edge, as shown in

th falling edge, having being clocked out on the previous

(13th) falling edge. It may also be possible to read in data on

each SCLK rising edge depending on the SCLK frequency or

the supply voltage. The first rising edge of SCLK after the

Figure 41

at Point B. If a 16-SCLK transfer is used, then two trailing zeros

will appear after the final LSB. On the rising edge of

falling edge would have the second leading zero provided, and

the 13

CS, the

conversion is terminated and DOUTA and DOUTB go back into

three-state. If

th rising SCLK edge would have DB0 provided.

CS is not brought high but is instead held low for

a further 14 (or 16) SCLK cycles on D

Note that with fast SCLK values, and thus short SCLK periods,

in order to allow adequately for t

OUT

A, the data from Con-

version B is output on DOUTA (followed by 2 trailing zeros).

, an SCLK rising edge may

occur before the first SCLK falling edge. This rising edge of

SCLK can be ignored for the purposes of the timing descriptions in

this section. If a falling edge of SCLK is coincident with the

falling edge of

Likewise, if

is held low for a further 14 (or 16) SCLK cycles

on D

B, the data from Conversion A is output on D

OUT

B. This

is illustrated in Figure 42 where the case for DOUTA is shown. In

this case, the D

CS, then this falling edge of SCLK is not

acknowledged by the AD7265, and the next falling edge of

SCLK will be the first registered after the falling edge of

OUT

line in use goes back into three-state on the

32nd SCLK falling edge or the rising edge of CS, whichever

occurs first.

CS.

SCLK

DOUTA

DOUTB

2 LEADING ZEROS

THREE-

STATE

tQUIET

THREE-STATE

DB11

DB10

DB2

DB0

DB1

DB9

DB8

Figure 41. Serial Interface Timing Diagram

SCLK

DOUTA

THREE-

STATE

THREE-

STATE

ZERO

DB11B

2 LEADING ZEROS

t10

DB11A

2 LEADING

ZEROS

DB10A

DB9A

ZERO

2 TRAILING ZEROS

ZERO

2 TRAILING ZEROS

Figure 42. Reading Data from Both ADCs on One D

Line with 32 SCLKs

OUT

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