EP3C5 datasheet(71/274 Pages) ALTERA

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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

5–11

Clock Feedback Modes

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Figure 5–7 shows the external clock outputs for PLLs.

Each pin of a differential output pair is 180° out of phase. The Quartus II software

places the NOT gate in your design into the I/O element to implement 180° phase

with respect to the other pin in the pair. The clock output pin pairs support the same

I/O standards as standard output pins (in the top and bottom banks) as well as LVDS,

LVPECL, differential HSTL, and differential SSTL.

f To determine which I/O standards are supported by the PLL clock input and output

pins, refer to the I/O Features in the Cyclone III Device Family chapter.

Cyclone III device family PLLs can drive out to any regular I/O pin through the

GCLK. You can also use the external clock output pins as general purpose I/O pins if

external PLL clocking is not required.

Clock Feedback Modes

Cyclone III device family PLLs support up to four different clock feedback modes.

Each mode allows clock multiplication and division, phase shifting, and

programmable duty cycle.

Figure 5–7. External Clock Outputs for PLLs

Notes to Figure 5–7:

(1) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.

(2) PLL#_CLKOUTp and PLL#_CLKOUTn pins are dual-purpose I/O pins that you can use as one single-ended or one

differential clock output.

PLL #

clkena 1

(1)

clkena 0

(1)

PLL #_CLKOUTp

(2)

PLL #_CLKOUTn

(2)

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