EP3C5 datasheet(22/274 Pages) ALTERA

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Chapter 1: Cyclone III Device Family Overview

Cyclone III Device Family Architecture

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

The hot socketing feature allows you to use FPGAs on PCBs that also contain a

mixture of 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V devices. The Cyclone III device family

hot socketing feature eliminates power-up sequence requirements for other devices

on the board for proper FPGA operation.

f For more information about hot socketing and power-on-reset, refer to the

Hot-Socketing and Power-on Reset in the Cyclone III Device Family chapter.

SEU Mitigation

Cyclone III LS devices offer built-in error detection circuitry to detect data corruption

due to soft errors in the CRAM cells. This feature allows CRAM contents to be read

and verified to match a configuration-computed CRC value. The Quartus II software

activates the built-in 32-bit CRC checker, which is part of the Cyclone III LS device.

f For more information about SEU mitigation, refer to the SEU Mitigation in the

Cyclone III Device Family chapter.

JTAG Boundary Scan Testing

Cyclone III device family supports the JTAG IEEE Std. 1149.1 specification. The

boundary-scan test (BST) architecture offers the capability to test pin connections

without using physical test probes and captures functional data while a device is

operating normally. Boundary-scan cells in the Cyclone III device family can force

signals onto pins or capture data from pins or from logic array signals. Forced test

data is serially shifted into the boundary-scan cells. Captured data is serially shifted

out and externally compared to expected results. In addition to BST, you can use the

IEEE Std. 1149.1 controller for the Cyclone III LS device in-circuit reconfiguration

(ICR).

f For more information about JTAG boundary scan testing, refer to the IEEE 1149.1

(JTAG) Boundary-Scan Testing for the Cyclone III Device Family chapter.

Quartus II Software Support

The Quartus II software is the leading design software for performance and

productivity. It is the only complete design solution for CPLDs, FPGAs, and ASICs in

the industry. The Quartus II software includes an integrated development

environment to accelerate system-level design and seamless integration with leading

third-party software tools and flows.

The Cyclone III LS devices provide both physical and functional separation between

security critical design partitions. Cyclone III LS devices offer isolation between

design partitions. This ensures that device errors do not propagate from one partition

to another, whether unintentional or intentional. The Quartus II software design

separation flow facilitates the creation of separation regions in Cyclone III LS devices

by tightly controlling the routing in and between the LogicLock regions. For ease of

use, the separation flow integrates in the existing incremental compilation flow.

f For more information about the Quartus II software features, refer to the Quartus II

Handbook.

EP3C5 Datasheet(PDF) 22 Page - Altera Corporation

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