EP3C5 datasheet(76/274 Pages) ALTERA

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5–16

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Hardware Features

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

Post-Scale Counter Cascading

Cyclone III device family PLLs support post-scale counter cascading to create

counters larger than 512. This is implemented by feeding the output of one C counter

into the input of the next C counter, as shown in Figure 5–12.

When cascading counters to implement a larger division of the high-frequency VCO

clock, the cascaded counters behave as one counter with the product of the individual

counter settings.

For example, if C0 = 4 and C1 = 2, the cascaded value is C0 × C1 = 8.

1 Post-scale counter cascading is automatically set by the Quartus II software in the

configuration file. Post-scale counter cascading cannot be performed using the PLL

reconfiguration.

Programmable Duty Cycle

The programmable duty cycle allows PLLs to generate clock outputs with a variable

duty cycle. This feature is supported on the PLL post-scale counters. You can achieve

the duty cycle setting by a low and high time count setting for the post-scale counters.

The Quartus II software uses the frequency input and the required multiply or divide

rate to determine the duty cycle choices. The post-scale counter value determines the

precision of the duty cycle. The precision is defined by 50% divided by the post-scale

counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty

cycle choices between 5 to 90%.

Combining the programmable duty cycle with programmable phase shift allows the

generation of precise non-overlapping clocks.

Figure 5–12. Counter Cascading

VCO Output

EP3C5 Datasheet(PDF) 76 Page - Altera Corporation