MCP25020ISLASHP datasheet(35/66 Pages) MICROCHIP

35 / 66 page

DS21664D-page 35

MCP2502X/5X

OPTREG2 REGISTER

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH GPIO MODULE

R/W-0

CAEN

ERREN

TXONEN

SLPEN

MTYPE

PDEFEN

PUSLP

PUNRM

bit 7

bit 0

bit 7

CAEN: Command Acknowledge Enable bit

= Enables the command acknowledge message (TXID1)

= Enables the receive overflow message (TXID1)

bit 6

ERREN: Error Recovery Enable bit

= MCP2502X/5X will recover into Listen-only mode from bus off

= MCP2502X/5X will recover into Normal mode from bus-off

bit 5

TXONEN: Transmit on Error Condition bit(REC or TEC)

= Enable, will send message if error counter(s) go high enough

= Disable, will NOT send message regardless of error counter values

bit 4

SLPEN: Low power SLEEP mode enable/disable

= Device will enter Sleep if bus is idle for at least 1408 bit times

= SLEEP mode is disabled

bit 3

MTYPE: Determines if information request messages use RTR or not

= RTR is NOT used for IRM (Data Frame)

= RTR is used for IRM (Remote Frame)

bit 2

PDEFEN: Enables PWM outputs to return to POR default values when CAN bus communication

is lost

= Enables PWM output default values

= Disables PWM output default values

bit 1

PUSLP: Allows device to enter SLEEP while in Listen-only mode during power-up sequence

= Enables SLEEP when in Listen-only mode during power-up sequence

= Disables SLEEP when in Listen-only mode during power-up sequence

bit 0

PUNRM: Enters Normal mode after completing self-configuration during power-up sequence

= Enters “Normal” mode after completing self-configuration during power-up sequence

= Enables “Listen-only” mode after completing self-configuration during power-up sequence

and waits for an error-free message before switching to Normal mode

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Addr

Name

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Value on

POR

Value on

RST

Bank 0

34h

GPDDR

—

DDR6

DDR5

DDR4

DDR3

DDR2

DDR1

DDR0

-111 1111

00h

IOINTEN

GP7TXC

GP6TXC

GP5TXC

GP4TXC

GP3TXC

GP2TXC

GP1TXC

GP0TXC

0000 0000

01h

IOINTPO

GP7POL

GP6POL

GP5POL

GP4POL

GP3POL

GP2POL

GP1POL

GP0POL

0000 0000

04h

OPTREG1

GPPU

CLKEN

CLKPS1

CLKPS0

—

CMREQ

AQT1

AQT0

0000 ----

Legend: x = unknown, U = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by module.

MCP25020I/P Datasheet(PDF) 35 Page - Microchip Technology

MCP25020I/P Datasheet(HTML) 35 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL