MCP25020ISLASHP datasheet(6/66 Pages) MICROCHIP

6 / 66 page

MCP2502X/5X

DS21664D-page 6

2.1

CAN Protocol Finite State Machine

The heart of the engine is the Finite State Machine

(FSM).

This

state

machine

sequences

through

messages on a bit-by-bit basis, changing states as the

fields of the various frame types are transmitted or

received. The FSM is a sequencer controlling the

sequential data stream between the TX/RX Shift

also controls the Error Management Logic (EML) and

the parallel data stream between the TX/RX Shift

registers and the buffers. The FSM insures that the pro-

cesses of reception, arbitration, transmission and error

signaling are performed according to the CAN protocol.

The automatic retransmission of messages on the bus

line is also handled.

2.2

Cyclic Redundancy Check (CRC)

The Cyclic Redundancy Check register generates the

Cyclic Redundancy Check (CRC) code that is

transmitted after either the Control field (for messages

with 0 data bytes) or the Data field and is used to check

the CRC field of incoming messages.

2.3

Error Management Logic

The error management logic is responsible for the fault

confinement of the CAN device. Its two counters (the

Receive Error Counter (REC) and the Transmit Error

Counter (TEC)) are incremented and decremented by

commands from the Bit Stream processor. According to

the values of the error counters, the MCP2502X/5X is

set into the states error-active, error-passive or bus-off.

Error-active: Both error counters are below the error-

passive limit of 128.

Error-passive: At least one of the error counters (TEC

or REC) equals or exceeds 128.

Bus-off: The transmit error counter (TEC) equals or

exceeds the bus-off limit of 256. The device remains in

this state until the bus-off recovery sequence is

received. The bus-off recovery sequence consists of

128 occurrences of 11 consecutive recessive bits.

FIGURE 2-2:

ERROR MODES STATE DIAGRAM

Note:

The MCP2502X/5X, after going bus-off,

will

recover

back

error-active

automatically if the bus remains idle for

128 x 11 bits. OPTREG2.ERRE must be

set to force the MCP2502X/5X to enter

Listen-only mode instead of Normal mode

during bus recovery. The current error

mode

(except

for

bus-off)

the

MCP2502X/5X can be determined by

reading the EFLG register via the Read

CAN error message.

Bus-Off

Error-Active

Error-Passive

REC < 127 or

TEC < 127

REC > 127 or

TEC > 127

TEC > 255

RESET

128 occurrences of

11 consecutive

“recessive” bits

MCP25020I/P Datasheet(PDF) 6 Page - Microchip Technology

MCP25020I/P Datasheet(HTML) 6 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL