MCP25020ISLASHP datasheet(19/66 Pages) MICROCHIP

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DS21664D-page 19

MCP2502X/5X

3.0

USER REGISTERS

3.1

Description

The MCP2502X/5X allows the user to pre-program

registers pertaining to CAN module and device

configuration into non-volatile EPROM memory. In this

way, the device is initialized to a default state after

power-up. The user registers are transferred to SRAM

during the power-up sequence and many of the

registers are able to be accessed via the CAN bus once

the device establishes a connection with the bus.

Additionally, there are 16 user-defined registers that

can be used to store information about the part (e.g.,

serial number, node identifier, etc.). The registers are

summarized in Table 3-1.

Note 1: When transferred to RAM, the register

addresses are offset by 1Ch. Accessing

individual

registers

using

the

“Write

requires use of the offset address. Also,

see

Table 3-2

for

information

accessible registers not contained in user

EPROM.

2: Do not address locations outside of the

user memory map or unexpected results

may occur.

TABLE 3-1:

USER MEMORY MAP

Address

Name

Description

Address

Name

Description

00h

IOINTEN

Enable inputs for Transmit-On-Change

feature

1Bh

RXF0EID0

Acceptance Filter 0, Extended ID

LSB

01h

IOINTPO

Defines polarity for I/O or greater than/

less than operator for A/D Transmit-On-

Change inputs

1Ch

RXF1SIDH

Acceptance Filter 1, Standard ID

MSB

02h

GPLAT

General Purpose I/O (GPIO) Register

1Dh

RXF1SIDL

Acceptance Filter 1, Standard ID

LSB, Extended ID USB, and

Extended ID enable

03h

0xFF

Reserved

1Eh

RXF1EID8

Acceptance Filter 1, Extended ID

MSB

04h

OPTREG1

Configuration options, including GPIO

pull-up enable, clockout enable and

prescaler

1Fh

RXF1EID0

Acceptance Filter 1, Extended ID

LSB

05h

T1CON

PWM1 Timer Control Register; contains

enable bit, clock prescale and DC LSBs

20h

TXID0SIDH

Transmit Buffer 0, Standard ID MSB

06h

T2CON

PWM2 Timer Control Register; contains

enable bits, clock prescale and DC LSBs

21h

TXID0SIDL

Transmit Buffer 0, Standard ID LSB,

Extended ID USB, and Extended ID

enable

07h

PR1

PWM1 Period Register

22h

TXID0EID8

Transmit Buffer 0, Extended ID MSB

08h

PR2

PWM2 Period Register

23h

TXID0EID0

Transmit Buffer 0, Extended ID LSB

09h

PWM1DCH PWM1 Duty Cycle (DC) MSBs

24h

TXID1SIDH

Transmit Buffer 1, Standard ID MSB

0Ah

PWM2DCH PWM2 Duty Cycle (DC) MSBs

25h

TXID1SIDL

Transmit Buffer 1, Standard ID LSB,

Extended ID USB, and Extended ID

enable

0Bh

CNF1 3

CAN module register configures

synchronization jump width and baud rate

prescaler

26h

TXID1EID8

Transmit Buffer 1, Extended ID MSB

0Ch

CNF2 3

CAN module register configures

propagation segment, phase segment 1,

and determines number of sample points

27h

TXID1EID0

Transmit Buffer 1, Extended ID LSB

0Dh

CNF3 3

CAN module register configures phase

buffer segment 2, Sleep mode

28h

TXID2SIDH

Transmit Buffer 2, Standard ID MSB

Note

GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch.

User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via “Read User Mem”

commands.

Cannot be modified from initial programmed values.

Unimplemented on MCP2502X devices and read 0x00 (exception, ADCON1 = 0x0F).

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