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AS3661

Datasheet - D e t a i l e d D e s c r i p t i o n

8.8 I2C Compatible Control Interface

The AS3661 supports the I

2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a

device receiving data as a receiver. The device that controls the message is called a master. The devices that are

controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the

bus access, and generates the START and STOP conditions must control the bus. The AS3661 operates as a slave on

the I

2C bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode (400kHz

maximum clock rate) are defined. The AS3661 works in both modes. Connections to the bus are made through the

open-drain I/O lines SDA and SCLTable 5

8.8.1 I

2C Address selection

The slave address can be selected depending on the connection of the two address selection pins ASEL0 and ASEL1.

The selected address for reading and writing depending on the state of ASEL0 and ASEL1 can be found inTable 5

below.

The following bus protocol has been defined (Figure 25):

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line

while the clock line is HIGH are interpreted as control signals.

Accordingly, the following bus conditions have been defined:

8.8.2 Bus Not Busy

Both data and clock lines remain HIGH.

8.8.3 Start Data Transfer

A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.

8.8.4 Stop Data Transfer

A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.

8.8.5 Data Valid

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of

the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal.

There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes

transferred between START and STOP conditions are not limited, and are determined by the master device. The

information is transferred byte-wise and each receiver acknowledges with a ninth bit.

8.8.6 Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The

master device must generate an extra clock pulse that is associated with this acknowledge bit.

Table 5. Chip Address Configuration

ASEL1

ASEL0

Address

8 bit Hex Address

(Hex)

R/W

GND

64/65

GND

VEN

66/67

VEN

GND

68/69

VEN

6A/6B

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