AS3661 datasheet(52/87 Pages) AMSCO

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AS3661

Datasheet - D e t a i l e d D e s c r i p t i o n

8.10.8 MISC

This register contains miscellaneous control bits like the clock detection. Program execution is clocked with internal

32.7 kHz clock or with external clock. External clock can be used if a clock signal is present on CLK-pin. The external

clock frequency must be 32.7 kHz in oder to meet the timing specifications of the datasheet and for correct operation.

If a higher or a lower frequency is used, it will affect on the program execution engine operation speed. The detector

block does not limit the maximum frequency. External clock status can be checked with read only bit EXT_CLK_USED

in register address 3A, when the external clock detection is enabled (Bit [1] CLK_DET_EN = high).

If external clock is not used in the application, CLK pin should be connected to GND to avoid oscillation on this pin and

extra current consumption.

Table 41. OUTPUT ON/OFF CONTROL LSB Register

OUTPUT ON/OFF CONTROL LSB

Bit

Bit Name

Default

Access

Bit Description

VARIABLE_D_SEL

R/W

The variable D can be linked to two different sources. The

default source for variable D is register 0x3C but it can be

assigned to the LED test ADC output. This allows, for example,

program execution control with an analog signal.

0: variable D source is register 0x3C

1: variable D source is LED test ADC.

EN_AUTO_INCR

R/W

The automatic increment feature of the serial bus address

enables a quick memory write of successive registers within

one transmission.

0: serial bus address automatic increment is disabled.

1: serial bus address automatic increment is enabled.

POWERSAVE_EN

R/W

Please refer to section 8.14.9 for a detailed description of the

powersave mode of AS3661.

0: power save mode is disabled.

1: power save mode is enabled.

4:3

CP_MODE

R/W

This register bits control the operation mode of the integrated

charge pump. The charge pump can be switched off, forced to

bypass mode, forced to 1.5x mode and automatic operation.

00: CP is switched off.

01: CP is forced to bypass mode (1x).

10: CP is forced to 1.5x mode (output voltage is 4.5V)

11: CP is in automatic mode depending on load conditions

PWM_PS_EN

R/W

For a detailed description of this power save mode please refer

to section 8.14.10. This mode can only be used if the CP is in

off mode or 1x mode.

0: PWM power save mode disabled.

1: PWM power save mode enabled.

CLK_DET_EN

R/W

The following bits define the clock selection of AS3661.

00: forced external clock (CLK pin).

01: forced internal clock.

10: automatic clock selection.

11: internal clock.

INT_CLK_EN

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