DOC7707 datasheet(179/307 Pages) ETC1

179 / 307 page

179

7707F–AVR–11/10

AT90USB82/162

18.5.1

Transmitter and Receiver Flags and Interrupts

The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode

are identical in function to the normal USART operation. However, the receiver error status flags

(FE, DOR, and PE) are not in use and is always read as zero.

18.5.2

Disabling the Transmitter or Receiver

The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to

the normal USART operation.

18.6

USART MSPIM Register Description

The following section describes the registers used for SPI operation using the USART.

18.6.1

USART MSPIM I/O Data Register - UDRn

The function and bit description of the USART data register (UDRn) in MSPI mode is identical to

normal USART operation. See “USART I/O Data Register n– UDRn” on page 165.

18.6.2

USART MSPIM Control and Status Register n A - UCSRnA

•

• Bit 7 - RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be

used to generate a Receive Complete interrupt (see description of the RXCIEn bit).

• Bit 6 - TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see

description of the TXCIEn bit).

• Bit 5 - UDREn: USART Data Register Empty

The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn

is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a

Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to

indicate that the Transmitter is ready.

• Bit 4:0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnA is written.

Bit

765

RXCn

TXCn

UDREn

UCSRnA

Read/Write

R/W

Initial Value

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