DOC7707 datasheet(37/307 Pages) ETC1

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7707F–AVR–11/10

AT90USB82/162

Figure 6-6.

PLL Clocking System

6.9.2

PLL Control and Status Register – PLLCSR

• Bit 7..5 – Res: Reserved Bits

These bits are reserved bits in the AT90USB82/162 and always read as zero.

• Bit 4..2 – PLLP2:0 PLL prescaler

These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the

PLL.

• Bit 1 – PLLE: PLL Enable

When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL

reference clock. If PLL is selected as a system clock source the value for this bit is always 1.

XTAL2

XTAL1

XTAL

PLL

PLLE

Lock

Detector

PLOCK

clkUSB (48MHz)

PLL clock

Prescaler

System Clock

clk

8MHz

Ext.

Int RC

8MHz.

Clock Switch

Clock Mux (fuse)

Bit

$29 ($29)

PLLP2

PLLP1

PLLP0

PLLE

PLOCK

PLLCSR

Read/Write

R/W

Initial Value

0/1

Table 6-10.

PLL input prescaler configurations

PLLP2

PLLP1

PLLP0

Clock Division Factor

Reserved

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