DOC7707 datasheet(53/307 Pages) ETC1

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7707F–AVR–11/10

AT90USB82/162

• Selectable Time-out period from 16ms to 8s

• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

• Early warning after one Time-Out period reached, programmable Reset (see operating modes)

after 2 Time-Out periods reached.

Figure 9-8.

Watchdog Timer

The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator.

The WDT gives a early warning interrupt when the counter reaches a given time-out value. The

WDT gives an interrupt or a system reset when the counter reaches two times the given time-out

value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer

Reset - instruction to restart the counter before the time-out value is reached. If the system

doesn't restart the counter, an interrupt or system reset will be issued.

In Interrupt mode, the WDT gives an interrupt when the timer expires two times. This interrupt

can be used to wake the device from sleep-modes, and also as a general system timer. One

example is to limit the maximum time allowed for certain operations, giving an interrupt when the

operation has run longer than expected.

In System Reset mode, the WDT gives a reset when the timer expires two times. This is typically

used to prevent system hang-up in case of runaway code.

The third mode, Interrupt and System Reset mode, combines the other two modes by first giving

an interrupt and then switch to System Reset mode. This mode will for instance allow a safe

shutdown by saving critical parameters before a system reset.

In addition to these modes, the early warning interrupt can be enabled in order to generate an

interrupt when the WDT counter expires the first time.

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-

tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt

mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, altera-

tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE or

changing time-out configuration is as follows:

128kHz

OSCILLATOR

WDP0

WDP1

WDP2

WDP3

WATCHDOG

RESET

WDE

WDIF

WDIE

WDEWIE

MCU RESET

INTERRUPT

EARLY WARNING

INTERRUPT

CLOCK

DIVIDER

OSC/1

OSC/3

OSC/5

OSC/7

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