DOC7707 datasheet(88/307 Pages) ETC1

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7707F–AVR–11/10

AT90USB82/162

13. Timer/Counter0 and Timer/Counter1 Prescalers

Timer/Counter0 and 1 share the same prescaler module, but the Timer/Counters can have dif-

ferent prescaler settings. The description below applies to all Timer/Counters. Tn is used as a

general name, n = 0 or 1.

13.0.1

Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (f

CLK_I/O). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f

CLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or

CLK_I/O/1024.

13.0.2

Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the

Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by

the Timer/Counter’s clock select, the state of the prescaler will have implications for situations

where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is

enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from

when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles,

where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-

tion. However, care must be taken if the other Timer/Counter that shares the same prescaler

also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is

connected to.

13.0.3

External Clock Source

An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk

Tn). The

Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-

nized (sampled) signal is then passed through the edge detector. Figure 13-1 shows a functional

equivalent block diagram of the Tn synchronization and edge detector logic. The registers are

clocked at the positive edge of the internal system clock (clk

I/O). The latch is transparent in the

high period of the internal system clock.

The edge detector generates one clk

Tn pulse for each positive (CSn2:0 = 7) or negative (CSn2:0

= 6) edge it detects.

Figure 13-1. Tn/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the Tn pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Tn_sync

(To Clock

Select Logic)

Edge Detector

Synchronization

clk

I/O

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