DM163006 datasheet(238/320 Pages) MICROCHIP

238 / 320 page

PIC18C601/801

DS39541A-page 238

Advance Information

 2001 Microchip Technology Inc.

IORLW

Inclusive OR literal with WREG

Syntax:

[ label ]

IORLW k

Operands:

≤ k ≤ 255

Operation:

(WREG) .OR. k

→ WREG

Status Affected:

N,Z

Encoding:

0000

1001

kkkk

Description:

The contents of WREG are OR’ed

with the eight bit literal 'k'. The result

is placed in WREG.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal ’k’

Process

Data

Write to

WREG

Example:

IORLW

35h

Before Instruction

WREG

9Ah

After Instruction

WREG

0BFh

IORWF

Inclusive OR WREG with f

Syntax:

[ label ]

IORWF

f [,d [,a]]

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(WREG) .OR. (f)

→ dest

Status Affected:

N,Z

Encoding:

0001

00da

ffff

Description:

Inclusive OR WREG with register

'f'. If 'd' is 0, the result is placed in

WREG. If 'd' is 1, the result is

placed back in register 'f' (default).

If ’a’ is 0, the Access Bank will be

selected, overriding the BSR value.

If ’a’ is 1, the Bank will be selected

as per the BSR value.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

IORWF

RESULT, W

Before Instruction

RESULT =

13h

WREG

91h

After Instruction

RESULT =

13h

WREG

93h

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