DM163006 datasheet(283/320 Pages) MICROCHIP

283 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 283

PIC18C601/801

FIGURE 22-13:

EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

TABLE 22-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

75, 76

MSb

LSb

Bit6 - - - - - -1

MSb In

LSb In

Bit6 - - - -1

Note: Refer to Figure 22-4 for load conditions.

Param.

No.

Symbol

Characteristic

Min

Max Units

Conditions

TssL2scH,

TssL2scL

↓ to SCK↓ or SCK↑ input

TCY

—

TscH

SCK input high time

(Slave mode)

Continuous

1.25TCY + 30

—

71A

Single Byte

—

(Note 1)

TscL

SCK input low time

(Slave mode)

Continuous

1.25TCY + 30

—

72A

Single Byte

—

(Note 1)

TdiV2scH,

TdiV2scL

Setup time of SDI data input to SCK edge

100

—

73A

TB2B

Last clock edge of Byte1 to the 1st clock edge of

Byte2

1.5TCY + 40

—

(Note 2)

TscH2diL,

TscL2diL

Hold time of SDI data input to SCK edge

100

—

TdoR

SDO data output rise time

PIC18C601/801

—

PIC18LC601/801

—

TdoF

SDO data output fall time

—

TscR

SCK output rise time

(Master mode)

PIC18C601/801

—

PIC18LC601/801

—

TscF

SCK output fall time (Master mode)

—

TscH2doV,

TscL2doV

SDO data output valid after

SCK edge

PIC18C601/801

—

PIC18LC601/801

—

100

Note 1: Requires the use of parameter # 73A.

2: Only if parameter #s 71A and 72A are used.

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