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DM163006 Datasheet(PDF) 286 Page - Microchip Technology |
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DM163006 Datasheet(HTML) 286 Page - Microchip Technology |
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286 / 320 page  PIC18C601/801 DS39541A-page 286 Advance Information 2001 Microchip Technology Inc. FIGURE 22-16: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO SDI 70 71 72 82 SDI 74 75, 76 MSb Bit6 - - - - - -1 LSb 77 MSb In Bit6 - - - -1 LSb In 80 83 Note: Refer to Figure 22-4 for load conditions. TABLE 22-15: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic Min Max Units Conditions 70 TssL2scH, TssL2scL SS ↓ to SCK↓ or SCK↑ input TCY — ns 71 TscH SCK input high time (Slave mode) Continuous 1.25TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TscL SCK input low time (Slave mode) Continuous 1.25TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 — ns (Note 2) 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — ns 75 TdoR SDO data output rise time PIC18C601/801 — 25 ns PIC18LC601/801 — 45 ns 76 TdoF SDO data output fall time — 25 ns 77 TssH2doZ SS ↑ to SDO output hi-impedance 10 50 ns 78 TscR SCK output rise time (Master mode) PIC18C601/801 — 25 ns PIC18LC601/801 — 45 ns 79 TscF SCK output fall time (Master mode) — 25 ns 80 TscH2doV, TscL2doV SDO data output valid after SCK edge PIC18C601/801 — 50 ns PIC18LC601/801 — 100 ns 82 TssL2doV SDO data output valid after SS ↓ edge PIC18C601/801 — 50 ns PIC18LC601/901 — 100 ns 83 TscH2ssH, TscL2ssH SS ↑ after SCK edge 1.5TCY + 40 — ns Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. |
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