| Electronic Components Datasheet Search |
|
DM163006 Datasheet(PDF) 113 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
DM163006 Datasheet(HTML) 113 Page - Microchip Technology |
|
113 / 320 page ![]() 2001 Microchip Technology Inc. Advance Information DS39541A-page 113 PIC18C601/801 9.5 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bi-directional port. The corre- sponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATE register reads and writes the latched output value for PORTE. PORTE is an 8-bit port with Schmitt Trigger input buff- ers. Each pin is individually configurable as an input or output. PORTE is multiplexed with several peripheral functions (Table 9-9). PORTE is multiplexed with the system bus and is avail- able only when the system bus is disabled, by setting EBDIS bit in register MEMCON. When operating as the system bus, PORTE is configured as the high order byte of the address/data bus (AD15:AD8), or as the high order address byte (A15:A8), if address and data buses are de-multiplexed. EXAMPLE 9-5: INITIALIZING PORTE FIGURE 9-9: PORTE BLOCK DIAGRAM IN I/O MODE Note: On Power-on Reset, PORTE defaults to the system bus. CLRF PORTE ; Initialize PORTE by ; clearing output ; data latches CLRF LATE ; Alternate method ; to clear output ; data latches MOVLW 03h ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE1:RE0 as inputs ; RE7:RE2 as outputs Peripheral Out Select Data Bus WR LATE WR TRISE Data Latch TRIS Latch RD TRISE Q D Q CK QD EN Peripheral Data Out 0 1 Q D Q CK P N VDD VSS RD PORTE Peripheral Data In I/O pin(1) or WR PORTE RD LATE Schmitt Trigger Note 1: I/O pins have diode protection to VDD and VSS. TRIS Override Peripheral Enable TRIS OVERRIDE Pin Override Peripheral RE0 Yes External Bus RE1 Yes External Bus RE2 Yes External Bus RE3 Yes External Bus RE4 Yes External Bus RE5 Yes External Bus RE6 Yes External Bus RE7 Yes External Bus |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |