DM163006 datasheet(119/320 Pages) MICROCHIP

119 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 119

PIC18C601/801

9.7

PORTG, LATG, and TRISG

Registers

PORTG is a 5-bit wide, bi-directional port. The corre-

sponding data direction register is TRISG. Setting a

TRISG bit (= 1) will make the corresponding PORTG

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISG bit (= 0) will

make the corresponding PORTG pin an output (i.e., put

the contents of the output latch on the selected pin).

Read-modify-write operations on the LATG register

read and write the latched output value for PORTG.

PORTG is multiplexed with system bus control signals

ALE, OE, WRH, WRL and BA0. The WRH signal is the

only signal that is disabled and configured as a port pin

(RG3) during external program execution in 8-bit mode.

All other pins are by default, system bus control sig-

nals. PORTG can be configured as an I/O port by set-

ting EBDIS bit in the MEMCON register and when

execution is taking place in internal program RAM.

EXAMPLE 9-8:

INITIALIZING PORTG

FIGURE 9-14:

PORTG BLOCK DIAGRAM

IN I/O MODE

Note:

On Power-on Reset, PORTG defaults to

system bus signals.

CLRF

PORTG

; Initialize PORTG by

; clearing output

; data latches

CLRF

LATG

; Alternate method

; to clear output

; data latches

MOVLW

04h

; Value used to

; initialize data

; direction

MOVWF

TRISG

; Set RG1:RG0 as outputs

; RG2 as input

; RG4:RG3 as outputs

Data

Bus

WR LATG

WR TRISG

RD PORTG

Data Latch

TRIS Latch

RD TRISG

Schmitt

Trigger

Input

Buffer

I/O pin(1)

RD LATG

PORTG

Note 1: I/O pins have diode protection to VDD and VSS.

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